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Plotting the trend of scaling for TSMC's CMOS, we should be alarmed (though not surprised eventually), that scaling is indeed dwindling:
Note that the N3E (representing 3FF) CGP is not officially known, as the IEDM 2022 published result (45 nm) looks more like a reference for N3B, so is indicated as such.
While I don’t expect us to get a 2x density bump from a node again (until maybe the cfet era), I suppose it is also worth noting that we are at the end of the line for finFETs, and this is partially responsible for the weak scaling we are seeing. We saw a similar thing for the few nodes that came out pre HKMG and pre finFET. After conservative gen1s we saw 2x for TSMC, if memory serves a touch shy of 2x for Samsung, and 2.5x for intel. While I doubt it will be as extrodonary as that, I think it is safe to expect big density bumps for gen2 HNSs (at the very least big with respect to the current scaling environment).
That was definitely part of the reason, and that is why I said we are unlikely to see N1.4 2x N2 density. However a 1.4-1.8x does sound very reasonable to me.
Yes but not as aggressively as before. N3 and N2 are both around 25nm M0 pitch. Going to 20nm with high-NA or SALELE while not easy (not that anything in this industry has been easy since Denard scaling died) is doable. Enhanced copper schemes should be able to do the job at ~25nm just fine. But below that new metalization schemes would likely be needed. Things like adding a layer below M0/allowing the old M0 to drop past the new M0 (see Scotten's recent IMEC article) and BSPD allow for big improvements to cell height without shrinking metal pitches. While not related to the BEOL, the better channel control for HNSs will also allow for shorter gate lengths, and as a result lower cell widths.
