Arthur Hanson
Well-known member
It looks like TSMC is in the memory game but with onboard the chip memory. Does anyone have any opinions or thoughts where TSMC could take this technology?
TSMC and STT-MRAM Memory?
- Thread starter Arthur Hanson
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I think there are some pretty obvious benefits of TSMC getting into memory.
Memory itself is somewhat of a commodity, but being able integrate memory onto the same package as the SoC, or in some cases into the SoC itself, could be a differentiator with significant value to customers. The less room consumed by essential components, the bigger battery, and the more additional features to you can provide the market with.
Now I personally think integration on package makes more sense than into an SoC, because of the additional cost, complexity, and die size (and implicitly lower yields) that would result from trying to integrate memory into the SoC. And I also think most of the benefits of integration can be had by going on package instead of all the way into SoC integration, assuming you have some sort of high speed on package interconnect.
With that context in mind, you look at TSMCs moves into packaging, and it makes sense to integrate memory as the next logical step. And lo and behold, TSMC is working on a high speed on package interconnect.
https://www.hotchips.org/wp-content...b/HC28.23.511-16nm-256bit-Lin-TSMC.MS-V03.pdf
Memory itself is somewhat of a commodity, but being able integrate memory onto the same package as the SoC, or in some cases into the SoC itself, could be a differentiator with significant value to customers. The less room consumed by essential components, the bigger battery, and the more additional features to you can provide the market with.
Now I personally think integration on package makes more sense than into an SoC, because of the additional cost, complexity, and die size (and implicitly lower yields) that would result from trying to integrate memory into the SoC. And I also think most of the benefits of integration can be had by going on package instead of all the way into SoC integration, assuming you have some sort of high speed on package interconnect.
With that context in mind, you look at TSMCs moves into packaging, and it makes sense to integrate memory as the next logical step. And lo and behold, TSMC is working on a high speed on package interconnect.
https://www.hotchips.org/wp-content...b/HC28.23.511-16nm-256bit-Lin-TSMC.MS-V03.pdf
It was probably necessary for TSMC to do this as Samsung is offering MRAM & GlobalFoundries supposedly offering 22FDX (22 nm FD-SOI) eMRAM later this year. The fact that Samsung already has a customer (NXP Semi) and GlobalFoundries plans on having option this year feels like TSMC needs to up their game to me.
I know TSMC is currently on a roll right now but I somehow feel they really need to start making smart investments in newer technologies and strengthening their core businesses. While they probably weren't going to be able to buy Toshiba's NAND technology....it really seemed like a half-hearted attempt publicly. Morris Chang, himself, said that there were "a lot of good targets out there".
I know TSMC is currently on a roll right now but I somehow feel they really need to start making smart investments in newer technologies and strengthening their core businesses. While they probably weren't going to be able to buy Toshiba's NAND technology....it really seemed like a half-hearted attempt publicly. Morris Chang, himself, said that there were "a lot of good targets out there".
I had heard rumblings around the ecosystem that TSMC was looking to license MRAM technology but was later told that they would do it internally. TSMC is staffed with memory experts and the best tools so I see this as highly probable. TSMC however reacts to customer demand so that is the timeline, when customers need it.
Let's ask what could you do with working MRAM if you're Apple and weren't especially constrained by money.
- persistent storage? Not anything obviously interesting there. I'm unaware of how this is realistically better than flash for realistic Apple workloads and devices.
- replacement for DRAM? No-one seems to consider this reasonable yet. The cell sizes remain way too large.
- replacement for SRAM? hmm. Now we're getting somewhere interesting.
Two sorts of possibilities suggest themselves to me. One would be much larger on-chip LLC. A10 has a 4MiB LLC (apparently primarily for use by the GPU to reduce power talking to DRAM). A10X does not have such an LLC (presumably because making it large enough to match the size the larger 12.9" screen covers is not feasible, and the A10X's wider DRAM bus covers the desired GPU bandwidth). So perhaps an on-chip MRAM L3 could be of a capacity large enough to meet the GPU's needs? This might not improve GPU performance that much, but would save some power.
An alternative possibility might be a tightly coupled (off chip but on package) large L3 (or L4) cache conceptually like the eDRAM used by IRIS Pro. Now we're talking much larger, say 128MiB and we have the potential to not only perhaps speed up a reasonable fraction of CPU and GPU activity, but also to save a fair bit of power in terms of substantially reduced request out to DRAM. This sort of alternative would be a different kind of direction from the various mobile-targeted wide-memory solutions that have been proposed. You might win some (lower latency), lose some (you don't get the high bandwidth when you miss the MRAM cache), and final net power is unclear, though presumably is lower for the MRAM solution if we believe everything we've been told.
One advantage of this sort of path is that it allows use of the MRAM while not coupling it to all the other moving parts of getting 10nm and then 7nm up to speed --- the separate MRAM die could be manufactured in 20/22nm or 16nm or whatever makes the most sense.
Part of why this is difficult to predict is that Samsung and TSMC both, publicly, have seemed to talk about the MRAM they want to ship as being a better NAND, ie a persistent storage solution. But I don't see the rich market they believe they are attacking by going down that path --- the best they can offer phones is something as ridiculous as Intel's justifiably mocked 32-GiB "kicker" Optane SSDs that are supposed to act as a cache to boost the speed of a slow HD (and do so --- but at vastly higher cost than just using a flash SSD).
Sure, there is more to the world than phones, and there are markets where some on-chip persistent storage, meaning no need for a flash die, is useful --- but phones is where the money is right now.
To me, MRAM as an LLC that reduces the power used by DRAM accesses seems like a better path towards providing something the high-end market (ie the customers with money) are willing to pay for.
- persistent storage? Not anything obviously interesting there. I'm unaware of how this is realistically better than flash for realistic Apple workloads and devices.
- replacement for DRAM? No-one seems to consider this reasonable yet. The cell sizes remain way too large.
- replacement for SRAM? hmm. Now we're getting somewhere interesting.
Two sorts of possibilities suggest themselves to me. One would be much larger on-chip LLC. A10 has a 4MiB LLC (apparently primarily for use by the GPU to reduce power talking to DRAM). A10X does not have such an LLC (presumably because making it large enough to match the size the larger 12.9" screen covers is not feasible, and the A10X's wider DRAM bus covers the desired GPU bandwidth). So perhaps an on-chip MRAM L3 could be of a capacity large enough to meet the GPU's needs? This might not improve GPU performance that much, but would save some power.
An alternative possibility might be a tightly coupled (off chip but on package) large L3 (or L4) cache conceptually like the eDRAM used by IRIS Pro. Now we're talking much larger, say 128MiB and we have the potential to not only perhaps speed up a reasonable fraction of CPU and GPU activity, but also to save a fair bit of power in terms of substantially reduced request out to DRAM. This sort of alternative would be a different kind of direction from the various mobile-targeted wide-memory solutions that have been proposed. You might win some (lower latency), lose some (you don't get the high bandwidth when you miss the MRAM cache), and final net power is unclear, though presumably is lower for the MRAM solution if we believe everything we've been told.
One advantage of this sort of path is that it allows use of the MRAM while not coupling it to all the other moving parts of getting 10nm and then 7nm up to speed --- the separate MRAM die could be manufactured in 20/22nm or 16nm or whatever makes the most sense.
Part of why this is difficult to predict is that Samsung and TSMC both, publicly, have seemed to talk about the MRAM they want to ship as being a better NAND, ie a persistent storage solution. But I don't see the rich market they believe they are attacking by going down that path --- the best they can offer phones is something as ridiculous as Intel's justifiably mocked 32-GiB "kicker" Optane SSDs that are supposed to act as a cache to boost the speed of a slow HD (and do so --- but at vastly higher cost than just using a flash SSD).
Sure, there is more to the world than phones, and there are markets where some on-chip persistent storage, meaning no need for a flash die, is useful --- but phones is where the money is right now.
To me, MRAM as an LLC that reduces the power used by DRAM accesses seems like a better path towards providing something the high-end market (ie the customers with money) are willing to pay for.
Arthur Hanson
Well-known member
I was wondering if TSM which has already stated they are going to put this memory directly on other chips if they be developing a version of an Automata processor chip for a customer. With its small size and memory on board it would make a ground breaking smart phone chip. Apple has the money and needs something earth shattering to stay on top. I know TSM really knows how to keep a secret, when asking something that may be sensitive, they claim to be no nothing about it. I wish they would just say NDA instead, but I guess even that would be giving up to much information by their standards.