TSMC 2026 Technology Symposium Santa Clara 22 April 2026

[user nl]

I suppose Dan or others will soon report here extensively on the TSMC 2026 Technology Symposium for firsthand updates on their technological progress and breakthroughs, from transistor scaling to system integration. Gaining insights for SemiWiki readers that will unleash innovations and drive AI forward.

A first glimps in this reporting By Reuters this evening:

TSMC shows smaller, faster chips without a pricey new tool from ASML​

Stephen Nellis and Max A. Cherney


SANTA CLARA, California, April 22 (Reuters) - Taiwan Semiconductor Manufacturing Co on Wednesday showed its newest generation of chip manufacturing technology, saying it expects to be able to create ‌smaller, faster chips without requiring expensive new machines from ASML.

TSMC, the global giant that makes chips for ‌Nvidia, Apple and Google, among many others, showed two improvements of chipmaking technology: One called A13, which will go into production in 2029 and likely be used for artificial intelligence chips, and one called N2U, a more affordable option that can be used to make chips for phones and laptops, as well as AI chips.

For all of the technologies TSMC showed on Wednesday, it is planning to squeeze more gains out of its existing extreme-ultraviolet lithography (EUV) machines from Dutch supplier ASML, rather than move to a newer ‌generation of "high NA" EUV machines, which, at $400 ⁠million each, are roughly double the cost of the older machines.

"This is where I think our R&D has done exceptionally well in terms of leveraging existing EUV technology while setting an ⁠aggressive technology scaling roadmap," Kevin Zhang, deputy co-chief operations officer and senior vice president, told Reuters. "This is definitely a strength."

But the gains from smaller and faster chips are modest, and TSMC also showed plans for new technologies in stitching complex AI chips together, which is where analysts expect companies like Nvidia to get the most performance gains in coming years. Where current AI offerings ‌like Nvidia's Vera Rubin, which will come out this year and is made by TSMC, have two large computing chips and eight stacks of high-bandwidth memory, TSMC on Wednesday said that by 2028 it will have the ability to stitch together 10 large chips and 20 memory stacks.

Named after Intel CEO Gordon Moore, his eponymous law predicted that computing power would roughly double every two years while at the same time get cheaper. In recent years, some such as Nvidia's ‌CEO Jensen Huang have said that it no longer holds true.

TSMC is effectively extending Moore's law through the company's technology that stitches multiple chips together, according to Dan Hutcheson, vice chair of TechInsights.

"Moore’s law is morphing from a monolithic, single die in a package to multi-die in ‌a package," he said in an interview. "And that allows the power and performance gains."

But stitching together chips brings challenges of its own. The chips get hot as they operate, and the different materials used to package them together expand at different rates, creating a fresh set of challenges for chip designers.
Large chip packages can bend and crack, ‌which were issues for Nvidia's Rubin AI processor, according to Ian Cutress, chief analyst at consultancy More Than Moore.

"(TSMC) aren't addressing directly how they are solving those challenges," Cutress said.

(Reporting by Stephen Nellis and Max Cherney in Santa Clara, California; Editing by Stephen Coates)

 

[user nl]

TSMC Debuts A13 Technology at 2026 North America Technology Symposium​

Newest Node Pushes Density Scaling and Energy Efficiency to New Heights to Address Industry’s Most Demanding Applications​

SANTA CLARA, CA, Apr. 22, 2026 -- TSMC (TWSE: 2330, NYSE: TSM) today debuted its latest innovation in its most advanced process technology at the Company’s 2026 North America Technology Symposium. TSMC’s new A13 process is a direct shrink of its industry-leading A14 node announced in 2025, enabling even more compact and efficient designs to address insatiable customer demand in computational requirements for next-generation artificial intelligence, high performance computing (HPC), and mobile applications.

Representing TSMC’s commitment to continuous improvement, A13 provides 6% area savings from A14. Design rules are fully backward compatible with A14, enabling customers to quickly migrate their designs to TSMC’s latest nanosheet transistor technology. In addition, A13 delivers increased power efficiency and performance gains through design-technology co-optimization, and is scheduled to enter production in 2029, one year after A14.

A13 was one of many technology innovations highlighted at TSMC’s North America Technology Symposium in Santa Clara, California, which kicks off the event series around the world in the coming months. With the theme of “Expanding AI with Leadership Silicon,” the technology symposiums are TSMC’s largest annual customer events, showcasing the Company’s breakthroughs in technology development and manufacturing service.

“At TSMC, we understand our customers are always looking ahead to their next innovation and they come to us for a reliable stream of new silicon technologies, like A13, meticulously engineered to be ready for high-volume production right when their visionary new designs demand them,” said TSMC Chairman and CEO Dr. C.C. Wei. “TSMC’s advanced process technologies lead the industry in density, performance and power efficiency, and we continually strive to make them even better for our customers’ future products, ensuring customers’ success as their most reliable technological partner."

Other new technologies unveiled at the North America Technology Symposium include:

Advanced Logic

• At the event, TSMC is also previewing its A14 platform enhancement A12, which features Super Power Rail technology to provide backside power delivery for AI and HPC applications. A12 is also scheduled to enter production in 2029.
• TSMC continues to advance its 2nm platform with the introduction of N2U, which employs design-technology co-optimization to reach speed gains of 3-4% or power reduction of 8-10% and a 1.02-1.03X logic density improvement from N2P. A balanced option for AI, HPC, and mobile applications leveraging the process maturity and strong yield performance of the 2nm technology platform, N2U is scheduled for production in 2028.

TSMC 3DFabric® Advanced Packaging and 3D Silicon Stacking

• To support AI demand for more computing power and memory in a single package, TSMC continues to expand its Chip on Wafer on Substrate (CoWoS®) technology to integrate more silicon. The Company is now producing 5.5-reticle size CoWoS and planning for even larger versions. A 14-reticle size CoWoS, capable of integrating approximately 10 large compute dies and 20 HBM stacks, is slated for production in 2028. This will be followed by an expansion to beyond 14 reticles in 2029. These new offerings provide customers with more options for AI compute scaling and complement TSMC’s 40-reticle size SoW-X System-on-Wafer technology also expected in 2029.
• TSMC is also offering its TSMC-SoIC® 3D chip stacking technology on its most advanced technology platform, with A14-to-A14 SoIC set to be available for production in 2029. It will provide 1.8X higher die-to-die I/O density compared with N2-on-N2 SoIC, supporting higher bandwidth of data transfer between stacked chips.
• TSMC’s Compact Universal Photonic Engine (TSMC-COUPE™) is set to reach a key milestone with a true co-packaged optics solution using COUPE on substrate beginning production in 2026. By integrating the COUPE optical engine directly inside the package, TSMC achieves 2X power efficiency and 10X latency reduction versus a pluggable version on the circuit board. The technology is featured in a 200Gbps micro-ring modulator, a highly compact and energy-efficient solution to move data between racks in data centers.

Automotive and Robotics

• Advanced Driver Assistance Systems (ADAS) and autonomous vehicles require leading-edge technologies along with stringent quality and reliability standards. Physical AI applications, such as humanoid robots, are adopting similarly demanding requirements. To address these needs, TSMC announced N2A, the first automotive-grade process technology with nanosheet transistors. N2A provides 15-20% speed gain at the same power compared with N3A and is scheduled to complete AEC-Q100 qualification in 2028. Furthermore, TSMC is making “Auto-Use” design kits available within its N2P process design kit (PDK), enabling customers to factor in automotive usage conditions in the design. This allows customers an earlier design start before N2A process is fully qualified.
• TSMC’s efforts to speed up automotive product cycles are already paying off for customers as N3A enters production in 2026. With the N3 “Auto Early” program, customers were able to start designs in 2023, and today more than 10 products are planned on N3A technology to make automobiles smarter, greener, and safer for consumers.

Specialty Technology

• TSMC is the first to bring high voltage technology into the FinFET era in 2026 with its N16HV process aimed at display driver applications. For smartphone display drivers, N16HV will increase gate density by 41% and reduce power by 35% compared to TSMC’s N28HV process. For near-eye displays, N16HV can shrink die area by 40% and reduce power by over 20%, enhancing the usability of applications such as smart glasses.

https://pr.tsmc.com/english/news/3302

 

[OneEng]

Wow. It is very interesting to see TSMC's take on the future scaling of processing.

If we modify Moore's law to "The number of transistors in a processor package" will double every 2 years, then this may even be possible now (for a time).

Where this thinking breaks down IMO is that the original Moore's law really MEANT that for the same PRICE you got double the transistors. That will most certainly NOT be true. I expect TSMC will charge cutting edge prices for this.

Even more interesting is how Intel appears to be betting heavily on High NA (keep shrinking the single die). Of course, Intel ALSO has "tiles" now, but seems like they are behind on stacking options (as I understand it) opting for a separate "tile" for bLLC designs while TSMC is moving beyond even vertical cache stacking to compute on compute stacking.

I propose a new law: "The cost of a new cutting edge processor will double every 2 years". Can I get this one named after me?