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The following essay was originally published on All Programmable Planet, but disappeared when that site was taken down. I have now re-edited and re-published it.
Most SoC design teams come up with a uniform RTL coding style, and can even use linting tools to enforce their style guidelines and rules on all team members.
Most SoC design teams come up with a uniform RTL coding style, and can even use linting tools to enforce their style guidelines and rules on all team members.
The article talked about a gray count sequence algorithm, RTL coding for an FSM to do gray counting in Verilog and VHDL, and how to think about writing RTL code. How we think about RTL effects the code style, and code styles can be checked and enforced.
The article talked about a gray count sequence algorithm, RTL coding for an FSM to do gray counting in Verilog and VHDL, and how to think about writing RTL code. How we think about RTL effects the code style, and code styles can be checked and enforced.
The message of the article is that coding styles are not neutral and may put an artificial and suboptimal limit on the available design solutions. For example, if one follows common Verilog coding guidelines ("do not use a blocking assignment in a clocked always block"), the presented design solution is not available.
