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The International Conference on Engineering of Reconfigurable Systems and Algorithms

Invited Talk: Self-Adaptive Embedded Systems

Invited Talk:

Distributed Approaches for Self-Adaptive Embedded Systems

Dr Pascal Benoit, Electrical Engineering department of University of Montpellier, France

Abstract:
In the recent years, there has been a growing interest in self-adaptive embedded systems.
Compared to the conventional approach, they require a control loop based on a three-step
process: (1) observation, handled by a set of sensors/monitors, (2) diagnosis, which analyzes
observed data to adapt the system, and (3) action, which tunes system parameters accordingly.
Putting an additional intelligence into the circuit so that it is capable of modifying itself
a set of parameters is not a new idea. But today, it seems that the conditions have been met to
build such circuits. Firstly, self-observation has been made feasible with different kind of
monitors, like activity counters, temperature sensors, critical path-monitors, etc. Secondly,
it is possible to tune the voltage/frequency pairs, to migrate the code of a given task from one
processing element to another, to adapt the routing of data in the interconnection network, etc.
So what is the real challenge today? Achieving a complex but realistic unified self-adaptation
mechanism, which strikes the balance between the introduced overhead, power consumption, performance
and area. Given the increasing complexity of embedded systems, our approach is to consider a regular
distributed architecture, with a set of identical Processing Elements, interconnected with a network
on chip. Thus, all the hardware/software building blocks required for self-adaptation, are the same
for each PE, which simplifies the scalability for future technologies. During this talk, we will
present an open experimental platform and original approaches for the control loop based on the
three-step adaptation process; we will analyze the cost of their implementation and will draw the
perspectives offered by such techniques.


bio:
Pascal Benoit obtained a Master Degree and PhD Degree in Electrical and Computer Engineering
from the University of Montpellier, France, in 2001 and 2004 respectively. Then, he joined the
Karlsruhe Institute of Technology in Germany where he has worked as a scientific assistant.
Since September 2005, he is a permanent Associate Professor at the University of Montpellier 2.
He teaches the design and programming of embedded systems (VHDL, C, C++, CAD Tools) at
the « Ecole Polytechnique Universitaire de Montpellier » and performs his research activities at
the LIRMM, the Montpellier Laboratory of Informatics, Robotics, and Microelectronics which is a
cross-faculty research entity of the University of Montpellier 2 (UM2) and the National Center
for Scientific Research (CNRS) - Department of Information and Engineering Sciences and
Technologies (IEST). He is involved in several national (ANR) projects (ADAM, Secresoc) and
european projects (ENIAC MODERN). Currently, he is the national head of the CRCC (CNFM) and
the manager of the industrial partnerships with the Electrical Engineering department of
Polytech’Montpellier. He has contributed to the organization of several international
conferences (IEEE ISVLSI 2008, IEEE SIES 2008, RCE, ReCoSoC, etc.) and was the Program Chair
of IEEE RAW/IPDPS in May 2011. His main research interests are reconfigurable and self-adaptive
systems, distributed optimization, monitoring techniques, and hardware security.
 
New relaxed deadlines

ERSA goes to WEB

New relaxed deadlines...


Conference Time Proceedings will be published on WEB


  • Late submission is open up to the End of June
  • We accept Academic and Industrial Papers
  • Proposals for panels and discussion sessions
  • Proposals for Demo and Exhibition

Despite the late deadline, try to make your submission and registration as early as possible


Final Edition of Proceedings


  • Camera-ready papers: August 20
  • Published in autumn
  • Hard-copy



For more, visit ERSA2012 web-site at ERSA'12 Conference Homepage
 
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National Instruments Corporation

Industrial Talk:

From Streaming Models to FPGA Implementations


Hugo Andrade, Jeff Correll, Amal Ekbal, Arkadeb Ghosal, Douglas Kim,
Jacob Kornerup, Rhishikesh Limaye, Ankita Prasad, Kaushik Ravindran,
Trung N Tran, Mike Trimborn, Gerald Wang, Ian Wong, Guang Yang

National Instruments Corporation, Berkeley, CA, USA


Abstract:
Application advances in the signal processing and
communications domains are marked by an increasing demand
for better performance and faster time to market. This has
motivated model-based approaches to design and deploy such applications
productively across diverse target platforms. Dataflow
models are effective in capturing these applications that are
real-time, multi-rate, and streaming in nature. These models
facilitate static analysis of key execution properties like buffer
sizes and throughput. There are established tools to generate
implementations of these models in software for processor targets.
However, prototyping and deployment on hardware targets, such
as FPGAs, are critical to the development of new applications.
FPGAs are increasingly used in computing platforms for high
performance streaming applications. Existing tools for hardware
implementation from dataflow models are limited in their capabilities.
To close this gap, we present DSP Designer, a framework
to specify, analyze, and implement streaming applications on
hardware targets. DSP Designer encourages a model-based design
approach starting from a Parameterized Cyclo-Static Dataflow
model. The back-end supports static analysis of execution properties
and generates implementations for FPGAs. It also includes
an extensive library of hardware actors and eases third-party IP
integration. Overall, DSP Designer is an exploration framework
that translates high-level algorithmic specifications to efficient
hardware. In this paper, we illustrate the modeling, analysis, and
implementation capabilities of DSP Designer. Through a detailed
case study, we show that DSP Designer is viable for the design of
next generation signal processing and communications systems.


View attachment 3798

FIG: National Instruments PXI Express Real-Time Signal Processing
Platform with Ettus Research RF Front-End.
 
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Harris Corporation

Industrial Talk:

Software-Based Reconfigurable Computing Platform (AppSTAR[SUP]TM[/SUP]) for Multi-Mission Payloads in
Spaceborne and Near-Space Vehicles


Dr. Edward R. Beadle and Dr. Tim Dyson
Harris Corporation
Government Communications Systems Division, Florida, USA

Abstract:
We present an on-demand rapidly reconfigurable (~seconds) software-defined payload (SDP) architecture called AppSTAR[SUP]TM[/SUP] with a core in-situ re-programmable processing capability that supports communications, radar, signal analysis and other missions. At the heart of Harris’ AppSTAR[SUP]TM[/SUP] SDP concept is a Virtex-based FPGA and interconnect fabric architecture that provides for a modular, flexible, scalable core capable of supporting a broad spectrum of missions with capabilities that can be customized for size, weight and power (SWaP) challenged platforms. Illustrating some of the capabilities evolving from this work, we present two real-world space qualified/qualifable SDPs, 1) a 100 Mbps-capable Ka-band software defined radio (SDR) for NASA and 2) a space-ready SAR/ISAR X-band RADAR based on the AppSTAR[SUP]TM[/SUP] core. We also present an application of this core in a payload for an operationally responsive space (ORS) payload. The work described herein primarily leverages our space qualified V4 Processor employing several FPGAs in excess of 1 million gates each. Related work offering dramatically increased integration, reducing the V4 Processor card to 1 cubic inch package suitable SWaP challenged near-space and terrestrial applications is also discussed.

View attachment 3800

FIG: Notional use case for reconfigurable payload
 
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Luna Innovations Incorporated

Industrial Keynote Talk:

Ensuring Design Integrity through Analysis of FPGA Bitstreams and IP Cores


Jonathan P. Graf, Scott H. Harper, and Lee W. Lerner
Luna Innovations Incorporated, Virginia, USA

Abstract:
In this paper, we introduce a novel, broad definition of field programmable gate array (FPGA) design integrity and explore its value in the domains of Trust, high-reliability design, and design anti-obsolescence for FPGA-based systems. We claim that an FPGA design with integrity must continuously provide the FPGA user with the function described by the designer and no other function. A common starting point for approaching design integrity in each of the explored domains is the FPGA bitstream. Luna’s unique software that evaluates the previously inaccessible designs inside of these bitstreams and third-party intellectual property (IP) provides a firm foundation for analysis of FPGA design integrity.

Presented by Jonathan P. Graf
 
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Prof. David Patterson

MAIN KEYNOTE

Prof. David Patterson, UC Berkeley, USA

Abstract:
 
Industrial Papers

Submission of industrial paper is yet open.

For industrial papers and talks:


  • submit extended abstract (half of page)
  • we do not require full paper, it is optional
  • the deadline for full papers is July 30, if you will choose this option

Make your submission as early as possible, if you are late, you may not have a time-slot available.

We may yet consider academic papers, but the time is running out, hurry, and contact with conf. at inf@ersaconf.org

For more details contact inf@ersaconf.org
 
Panel on Security

ERSA will have a Panel Discussion on Hardware Security

“Hardware security and trust in reconfigurable heterogeneous systems”

A wide range of applications relies on dedicated, embedded hardware platforms, which, in a most complex case, tend to be reconfigurable heterogeneous systems. The critical issue is the trusted and secure hardware design. The other critical issue is the intellectual-property protection.

The applications may range from Internet protocols, telecommunication systems, power grids, military systems, databases, and financial services, if to list some of these.

We will concentrate, but not limiting, on the following topics.


  • Design methodologies for secure and trusted hardware and software
  • Protection and identification techniques for IP cores
  • Trojan detection and hardware cryptography

If you are interested in participation, being a panel member, make a statement or short presentation, contact with us at inf@ersaconf.org

Send us abstract of your statement, presentation.

You can submit your proposals, comments, etc to this SemiWiki thread.
 
Deadline for Registration: July 5, 2012

[h=2]Deadline for Registration: July 5, 2012[/h]
To participate at ERSA, with paper or without paper, you have to register for ERSA conference at WorldComp website:

WORLDCOMP'12 Registration — WORLDCOMP12


Do not forget that you have to register for ERSA conference!

If you are interested in participation, being a panel member, make a statement or short presentation, contact with us at inf@ersaconf.org

Send us abstract of your statement, presentation.
Deadline: end of June.

Despite the late deadline, try to make your submission/proposal as early as possible.


To book your room in Hotel – Monte Carlo Resort, visit

WORLDCOMP'12 Venue / Accommodation — WORLDCOMP12


Important Note: TO QUALIFY FOR THE CONFERENCE RATE, ROOMS MUST BE RESERVED BY JUNE 27, 2012.
 
Panel on High Level Design

ERSA will have a Panel Discussion on High Level Design

“High Level Design for FPGAs: OpenCL, Space Codesign, Cuda ...”

A range of complex, intelligent embedded applications require high-performance systems implemented as multicore systems and heterogeneous parallel processing systems. This involves reconfigurable computing technologies across mobile, embedded, and HPC domains. For many applications, FPGAs are a tremendously efficient computational fabric. The traditional design systems use low-level Hardware Design Languages.

When it comes to developing complex heterogeneous systems, a level of abstraction that is closer to traditional software-centric approaches is required. Languages and design techniques high-level abstractions allow us to tradeoff some efficiency for added designer productivity. These techniques are coming more and more popular among design community.

In this discussion session, we will concentrate, but not limiting, on the following high-level design systems and languages.

  • OpenCL
  • Space Codesign
  • Cuda
If you are interested in participation, being a panel member, make a statement or short presentation, contact with us at inf@ersaconf.org

Send us abstract of your statement, presentation.
Deadline for abstract: end of June.
Full text, if you are interested, should be submitted after the conference, July 30.

You can submit your proposals, comments, etc to this SemiWiki thread.
 
Panel Discussions

If you have a good idea, you can yet make a proposal for discussion panel.
Contact: inf@ersaconf.org


Currently we have:

“Hardware security and trust in reconfigurable heterogeneous systems”
“High Level Design for FPGAs: OpenCL, Space Codesign, Cuda ...”
 
Hardware Security Session

[h=3]Hardware security and trust in reconfigurable heterogeneous systems[/h]Presentation Session

Keynote talk

Ensuring Design Integrity through Analysis of FPGA Bitstreams and IP Cores
Jonathan P. Graf, Scott H. Harper, and Lee W. Lerner
Luna Innovations Inc., USA

Invited Talk

Tackling the Security Issues of FPGA Partial Reconfiguration with Physical Unclonable Function
Dr. Yohei Hori, National Institute of Advanced Science and Technology, Japan

Regular Talks

Cryptanalysis on Reconfigurable Computers
Tim Güneysu, Horst Goertz Institute for IT-Security, Ruhr-Universitaet Bochum, Germany

NEW!!!
A Practical FPGA Implementation of Regular Expression Matching with Look-ahead Assertion

Yoichi Wakaba, Masato Inagi, Shin'ichi Wakabayashi
Hiroshima City University, Japan

Watermarking-Based Protection of Embedded Cores on FPL Devices
L. Parrilla*, E. Castillo*, A. García*, G. Botella**
* Dept. Electronics and Computer Technology, University of Granada, Granada, Spain
** Dept. of Computer Architecture and Automation, Complutense University of Madrid, Madrid, Spain


Panel Discussion Session

Chair: TBA


If you are interested in participation, being a panel member, make a statement or short presentation, contact with us at inf@ersaconf.org

Send us abstract of your statement, presentation.

You can submit your proposals, comments, etc to this SemiWiki thread.
 
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Hardware Security Panel

“Hardware security and trust in reconfigurable heterogeneous systems”


Panel Members

Jonathan Graf
Director of SCC Technologies, Secure Computing & Communications Group
Luna Innovations Incorporated, USA

Statement:

Globalization of the supply chain for microelectronic devices and design software presents
new challenges to defense developers who seek to guarantee the trusted operation of their
microelectronic systems. An important element of this challenge revolves around the trust
of Field Programmable Gate Array (FPGA) devices, due to their increasing use as the device
of choice for implementing critical defense functions. FPGAs are unique in that they are
programmed to accomplish these critical functions with a design file, called a bitstream,
which molds the device to become the custom computing machine appropriate to the specific
application of interest. Thus, the bitstream contains the critical FPGA function that must
be trusted. To trust the function of the FPGA, defense developers must be guaranteed that
the design contained in the bitstream does only what it is designed to do and nothing more.
However, there are two major factors that work against this guarantee. The first is that
the design software used to create the final bitstream that programs the FPGA is of unknown
provenance within the globalized software supply chain. The second is that the bitstream format
in which the design is contained has traditionally been an inaccessible black box whose contents
cannot be evaluated. To address these challenges, Luna has developed software called the Change
Detection Platform (CDP). First, it solves the problem of unlocking the bitstream, allowing
full evaluation of the final format in which the user’s design is represented. Next,
it performs an extensive evaluation that detects any differences between the user’s intent
and the actual function of the design contained in the bitstream.


Bio:

Jonathan Graf directs the research, development, and deployment of Luna’s Secure Computing and
Communications (SCC) technologies. He concentrates on FPGA design integrity solutions that ensure
design trust, enable high-reliability verification, migrate designs from obsolete FPGAs to modern
parts, and provide FPGA design and security analysis. At Luna, he has served in the role of
Principal Investigator and Project Manager for Luna’s prime contracts on two DARPA BAA programs
related to FPGA Trust: DARPA Trust and DARPA IRIS. He has also served as Principal Investigator
for 18 DoD SBIR projects. He is responsible for fostering Luna's SCC technologies from inception
to market in both defense and commercial arenas. Prior to Luna, Jonathan worked for Intel, Sprint,
and three small startups. In addition to ERSA, his publications and invited talks in the past
year have included the DoD Anti-Tamper Conference, the Microelectronic Circuit Analysis and
Reverse Engineering Conference, the Government Microcircuit Applications and Critical Technology
Conference, the Xilinx Safety and Reliability Consortium, the Army Research Office Workshop on
Hardware Assurance, and the corporate Anti-Tamper conferences for both Xilinx and Lockheed Martin.


If you are interested in participation, being a panel member, make a statement or short presentation, contact with us at inf@ersaconf.org

Send us abstract of your statement, presentation.

You can submit your proposals, comments, etc to this SemiWiki thread.
 
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High Level Design Session

[h=3]Developing heterogeneous systems (Multicore, CPU plus FPGA, …)[/h]
Presentation Session

Keynote talk (Altera)

Towards OpenCL Compilation into High-Performance Hardware for FPGAs

Prof. Stephen Brown, University of Toronto, Canada

Invited Paper

Distributed Approaches for Self-Adaptive Embedded Systems
Dr Pascal Benoit, Electrical Engineering department of University of Montpellier, France

Distinguished Paper

A Configurable VHDL Template for Parallelization of 3D Stencil Codes on FPGAs
Franz Richter, Michael Schmidt and Dietmar Fey,
FAU Erlangen-Nuremberg, Germany


Industrial Paper

From Streaming Models to FPGA Implementations
Hugo Andrade, Jeff Correll, Amal Ekbal, Arkadeb Ghosal, Douglas Kim,
Jacob Kornerup, Rhishikesh Limaye, Ankita Prasad, Kaushik Ravindran,
Trung N Tran, Mike Trimborn, Gerald Wang, Ian Wong, Guang Yang
National Instruments Corporation, USA


Regular Papers

Identifying Data-Dependent System Scenarios in a Dynamic Embedded System
Elena Hammari*, Francky Catthoor**, Per Gunnar Kjeldsberg*, Jos Huisken***, Konstantinos Tsakalis****, Leonidas Iasemidis****
* Norwegian University of Science and Technology, Norway
** Imec and K.U.Leuven, Belgium
*** Imec / Holst Centre, The Netherlands
**** Arizona State University, USA


Generic Synthesizable Hardware Platform for Multicore Architectures
Natwar Agrawal, Annie Avakian, Ranga Vemuri,
University of Cincinnati, USA



Panel Discussion Session

Chair: TBA


If you are interested in participation, being a panel member, make a statement or short presentation, contact with us at inf@ersaconf.org

Send us abstract of your statement, presentation.

You can submit your proposals, comments, etc to this SemiWiki thread.
 
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For ERSA Authors: final edition

[h=2]For ERSA Authors

Uploading final version for publisher[/h]
  • Official Edition of Proceedings in hard-copy will be published in Autumn
  • Deadline August 20: Authors should upload the final version of their paper(s)
  • Authors will receive the guidelines of submission/uploading their paper(s)
 
ERSA 2013 Preliminary CFP

ERSA'13

The 2013 International Conference on
ENGINEERING OF RECONFIGURABLE SYSTEMS AND ALGORITHMS -

July ..-.., 2013, Monte Carlo Resort, Las Vegas, Nevada, USA
ERSA-NEWS Website: ERSA News | The International Conference on Engineering of Reconfigurable Systems and Algorithms

[h=3]International Gathering for Commercial and Academic Reconfigurable Computing Application Developers[/h]ERSA emphasises the commercial and industrial challenges in reconfigurable technology

ERSA consists of two parts:

  • ERSA Academic
  • ERSA Industrial Session: Application Developers Forum
[h=3]What is hot: [/h][h=3]Design systems[/h]
  • [h=3]Heterogeneous Systems Architecture: Multicore, CPU plus FPGA, …
    [/h]
  • [h=3]High Level Design Tools for Heterogeneous Systems:
    [/h]
  • [h=3]OpenCL, SystemC, Space Codesign, Cuda, ... [/h]
  • Models of Embedded Reconfigurable Systems

[h=3]Security[/h]
  • [h=3]Hardware Security and Trust an Reconfigurable Heterogeneous Systems
    [/h]
  • [h=3]Cryptography[/h]
[h=3]Applications[/h]
  • [h=3]Application Development for Heterogeneous Run-time Environments
    [/h]
  • [h=3]Reconfigurable and Multicore Computing in Finance and Banking
    [/h]
  • [h=3]Monte Carlo Methods In Technical and Financial Systems
    [/h]
  • [h=3]Adaptable and Distributed Embedded Systems
    [/h]
  • [h=3]Reconfigurable Hardware Support for Internet
    [/h]
  • [h=3]Communication Systems in Government, Military, Space and Consumer Applications
    [/h]


Proposals for

  • [h=2]Panel Discussion Sessions
    [/h]
  • [h=2]Academic Sessions
    [/h]
  • [h=2]Industrial Sessions
    [/h]
  • [h=2]Demos and Exhibitions[/h]

Visit ERSA News at ERSA News | The International Conference on Engineering of Reconfigurable Systems and Algorithms

For more info and for proposals, contact with ERSA Chair Toomas Plaks at inf@ersaconf.org
 
The new, ERSA related journal will be launched shortly

[h=2]“Application Developers’ News:
Developers of Heterogeneous Computing Systems”
[/h]
Visit: Application Developers' News, Journal, ERSA


This journal will accept and publish strong, full size technical papers. It is not a commercial journal, nor an academic journal. It is a Journal for industrial researchers, entrepreneurs, and developers.

Scope: Developing Heterogeneous Reconfigurable Computing Systems for mobile, high-performance, low-power, and embedded applications

It will be published on monthly bases (in beginning), distributed by email, and in web.

For more, visit: Application Developers' News, Journal, ERSA


I would appreciate any feedback

Thanks, Toomas

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<script src="//platform.linkedin.com/in.js" type="text/javascript"></script>



<script type="IN/Share+init" data-url="http://ersaconf.org/ersa-news/ersa-developers-news.php" data-counter="right"></script>
 
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New Journal

Application Developers’ News
Developers of Heterogeneous Computing Systems


Visit Application Developers' News website.


The Application Developers News is a Journal for industrial researchers, entrepreneurs, and developers.

The Application Developers News publishes strong, full size peer-reviewed technical papers, which form the main content of journal. Acceptance based purely on the quality of the submissions. Journal will have ISBN number, and papers are indexed in main databases. Copyright remains with the author.

The Developers’ Journal will turn the ERSA conference into year-around event, and Las Vegas is just the meeting point of researchers.

In addition, we publish short technical papers, which may be technical notes, comments, technical overviews, including overviews of technical events and other similar short texts.

Along of technical papers, we accept advertisements of upcoming events, call for papers (CFP), and advertising from companies including job opportunities.

The journal will be published on monthly bases, distributed by email, and is available in web.

The basic service is free; it includes abstracts of full size technical papers, full texts of short technical papers and advertisements from companies. In email version we publish this in a reduced form, in journal website, all these texts are available and are free for everybody, except, full size technical papers.

The advanced service includes access to full technical papers; this is available in the members’ area of the Journal. It will cost a small membership fee.


Fees and charges

Sorry, not all fees and details are finally fixed


  • Membership fee will be $10 per month
  • Submission of full size papers for publications is charged by $1,000 for 10 pages in IEEE double-column transaction format, additional pages have extra charged
  • Submission of short papers for publications is charged by $500 for 5 pages
  • Advertising, company logo (plus link to their webpage): fee for one month is $500, for three months $1,200, for one year $2,500
  • Advertising, company logo plus product information or short company introduction (half page + one image): cost for one month is $800, for three months is $1,800, and for one year is $5,000
  • Negotiations are available for larger advertising space


Market penetration


We have around 50,000 - 60,000 web-based recipients of our messages. We use various email lists and professional networks, like SemiWiki, LinkedIn, etc.


The Scope of Application Developers’ News

The information age continues to surprise and challenge us all in the fast pace of evolving technology. As opportunities for heterogeneous reconfigurable technology continues to evolve, opportunities for low-power hybrid mobile computing, or challenges for ultra-efficient exascale computing, the need is now more than ever for a journal that bridges both leading-edge thinking with practical application.

Whether it be in health information, mobile devices, sensor grids, business analytics, cyber-security or scientific research, the new applications of computing technology continue to amaze with the possibilities.

Application Developers’ News focus on challenges, tools, available technologies and opportunities when it comes to developing and supporting applications, both academic and commercial, that involve reconfigurable computing technologies across mobile, embedded, and HPC domains.

The scope cover broad area, from simple applications on programmable logic to complex, intelligent, high-performance, embedded systems implemented as multicore systems and heterogeneous parallel processing systems. All these complex systems involve reconfigurability on software and/or hardware level.

Topics are not limited to the following:

Developing Heterogeneous Reconfigurable Computing Systems for mobile, high-performance, low-power, and embedded applications

Design systems


  • Heterogeneous Systems Architecture: Multicore, CPU plus FPGA, …
  • High Level Design Tools for Heterogeneous Systems:
    OpenCL, SystemC, Space Codesign, Cuda, ...
  • Models of Embedded Reconfigurable Systems

Applications

  • Application Development for Heterogeneous Run-time Environment
  • Hardware Security and Trust in Reconfigurable Heterogeneous Systems
  • Cryptography
  • Adaptable and Distributed Embedded Systems
  • Reconfigurable Hardware for Defence Industry
  • Reconfigurable Hardware Support for Internet
  • Communication Systems in Government, Military, Space and Consumer Applications
  • Automotive Industry
  • Bio-Inspired Architectures
  • Monte Carlo Methods in Technical and Financial Systems
  • Reconfigurable and Multicore Computing in Finance and Banking
  • High-Performance Embedded Systems
  • Mobile Computing Systems
  • Low-power Systems
  • Ultra-efficient Exascale Computing
  • ...
 
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First Issue in Feb. 2013

Application Developers' News

First Issue will be published in Feb. 2013

CALL FOR PAPERS

Submission Deadline: Dec. 20, 2012

For more details, contact by email: inf@ersaconf.org

Available Options


  • Submission of full size papers for publications is charged by $1,000 for 10 pages in IEEE double-column transaction format, additional pages have extra charged
  • Submission of short papers for publications is charged by $500 for 5 pages
  • Advertising, company logo (plus link to their webpage): fee for one month is $500, for three months $1,200, for one year $2,500
  • Advertising, company logo plus product information or short company introduction (half page + one image): cost for one month is $800, for three months is $1,800, and for one year is $5,000
  • Negotiations are available for larger advertising space

For more details, visit Application Developers' News website, or contact the Chair, Toomas Plaks by email: inf@ersaconf.org

Thanks,
Toomas
 
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