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Daniel, I predict SV12 is the next V2K. A year from now, except as an interchange format for netlists, Verilog without the System will only be used in "The Land that Time Forgot". It's either VHDL or SV12 from now on.
The next question for any language standard is what is the level of support by the EDA vendors. Does anyone have any thoughts on how supported it currently is in areas other than testbench/verification? The use of a language in a design flow is limited by the tool in the flow with the lowest level of support.
"The use of a language in a design flow is limited by the tool in the flow with the lowest level of support."
And your design flow is limited by your willingness to pay for the best tools both license fees and the internal support for upgrading legacy scripts. If you don't pay the premium for best-in-class tools, you'll eventually be left behind by your competitors. The legacy issues are usually grossly exaggerated for job security.
Interesting response to my comment, I think you are reading a little too much into my statement and perhaps we should start a new thread since we are going beyond the LRM. I was not saying that there was any legacy or cost issue involved in my observation but it seemed a true statement. Let's go ahead and say I am willing to pay for your "best-in-class" tools. Even with that, there may be something in my flow limiting me on the feature set of the language that is supported.
SystemVerilog adoption in the verification space is clear and market studies like Mentor's here The 2012 Wilson Research Group Functional Verification Study - Mentor Graphics show that clear trend and I am in favor of that. I was just trying to learn if it was also being adopted as a design language and how well it was being adopted and supported by tools such as synthesis, formal verification, linting, RTL power estimation, and similar front end and physical design tools that make up a complete design flow.
Nobody that writes big checks is still using Verilog for design, it's either VHDL or SV, so the flow is there. If the question is specifically SV12, there wasn't much added that was relevant to design except interface classes and generic interconnect. The interface classes aren't supported yet. Also, there was an endorsement by SV12 of using static methods from virtual classes to achieve the effect of parameterized functions, and I suppose all design tools support that by now.
