Samsung’s Backside Power Delivery Network Reportedly to Reduce 2nm Chip Size by 17%

[Daniel Nenni]

Intel is tipped to become the first chipmaker to apply the backside power delivery network to the 2-nanometer node

A new contract chipmaking technology, dubbed the backside power delivery network (BSPDN), will reduce the size of a 2-nanometer chip by 17%, compared with the traditional front-end power delivery technology, said Samsung Electronics Co.'s foundry business executive on Thursday.

The BSPDN, which Samsung is set to apply for mass production of the 2 nm process from 2027, also improves performance and power efficiency by 8% and 15%, respectively, compared to the chips with the front-end power delivery networks, said Lee Sungjae, vice president and Foundry PDK Development Team at Samsung.

He outlined the technological prowess of BSPDN in a keynote speech at Siemens EDA Forum 2024. It was the first time for a Samsung foundry business executive to give a detailed account of its BSPDN technology in public.

BSPDN is called a next-generation chip foundry technology. It places power rails on the back of the semiconductor wafer to eliminate bottlenecks between the power and signal lines, allowing for smaller chips.

Contract chipmakers are gearing up to adopt the advanced chipmaking process. Leading the pack, Intel plans to produce chips with BSPDN on the Intel 20A process, known as a 2 nm node, within the year. It dubbed its BSPDN technology as PowerVia.

TSMC, which controls 62% of the global foundry market, said it plans to introduce the BSPDN to its 1.6 nm and below process nodes around the end of 2026.

Samsung's advanced foundry process node roadmap unveiled at Samsung Foundry Forum (SFF) 2024
Lee also unveiled the roadmap and performance of chips to be made with the next-generation gate-all-around (GAA) technology that Samsung adopted in 2022 for the first time in the world.

It plans to mass-produce 3 nm chips based on the second-generation GAA technology (SF3) in the second half of this year and deliver GAA on its upcoming 2 nm process.

SF3 has improved chip performance and power efficiency by 30% and 50%, respectively, while reducing the chip size by 35%, compared with the chips produced on the first-generation GAA process, Lee added.

Samsung’s new 2 nm foundry process to cut chip size by 17% - KED Global

A new contract chipmaking technology, dubbed the backside power delivery network (BSPDN), will reduce the size of a 2-nanometer chip by 17%, compared with the

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[MKWVentures]

Everyone is talking about BSP. It will be interesting to see who actually delivers a product and when. It is very complicated and expensive. Can't wait to see cross sections in a actual product selling to consumers.

 

[Daniel Nenni]

Everyone is talking about BSP. It will be interesting to see who actually delivers a product and when. It is very complicated and expensive. Can't wait to see cross sections in a actual product selling to consumers.

Intel will be the first and AMD the second with TSMC's version. I would hope Intel's version will be the best implementation but we shall see. I have zero confidence in Samsung's version. I still have not found a Samsung 2nm design start and I am at conferences talking to the ecosystem and chip designers.

 

[Maximus]

Intel will be the first and AMD the second with TSMC's version. I would hope Intel's version will be the best implementation but we shall see. I have zero confidence in Samsung's version. I still have not found a Samsung 2nm design start and I am at conferences talking to the ecosystem and chip designers.

Samsung typically likes to boast about being the leader in new technology. If they’re saying BSPDN will be delivered in 2027, which is later than both Intel and TSMC, it indicates they are seriously lagging behind in the game.

 

[IanD]

I've seen numbers from TSMC showing area saving (and speed increase/power decrease) with BSPD (N2 vs. A16), and they strongly depend on the power grid density -- which in turn depends in the die power density (W/mm2) and chip design. The area savings can be up to >15% in the best case, but also down to <5% in the worst case. Power savings are maybe half these numbers.

What TSMC say is that BSPD (A16) is appropriate for high-power chips with active cooling -- high-power because for many chips with a less dense power grid the PPA savings are small, and active cooling because the thermal resistance from die to heatsink is bigger with BSPD, so the chip runs hotter, so you need a nice cool heatsink not a hot one.

There's also the wafer cost premium which is currently rather high to say the least, considerably bigger than even the most optimistic area saving.

So if your #1 priority is best possible PPA and smallest die and you have a high-power chip and active cooling and are willing to pay the cost premium, BSPD is great -- and it is a new sexy technology...

For many applications it's not, certainly in its first version in A16 -- and though cost will undoubtedly come down, the fundamental disadvantages will remain. As will the fundamental advantages, obviously... ;-)

 

[nghanayem]

I've seen numbers from TSMC showing area saving (and speed increase/power decrease) with BSPD (N2 vs. A16), and they strongly depend on the power grid density -- which in turn depends in the die power density (W/mm2) and chip design. The area savings can be up to >15% in the best case, but also down to <5% in the worst case. Power savings are maybe half these numbers.

What TSMC say is that BSPD (A16) is appropriate for high-power chips with active cooling -- high-power because for many chips with a less dense power grid the PPA savings are small, and active cooling because the thermal resistance from die to heatsink is bigger with BSPD, so the chip runs hotter, so you need a nice cool heatsink not a hot one.

There's also the wafer cost premium which is currently rather high to say the least, considerably bigger than even the most optimistic area saving.

So if your #1 priority is best possible PPA and smallest die and you have a high-power chip and active cooling and are willing to pay the cost premium, BSPD is great -- and it is a new sexy technology...

For many applications it's not, certainly in its first version in A16 -- and though cost will undoubtedly come down, the fundamental disadvantages will remain. As will the fundamental advantages, obviously... ;-)

The density story is highly dependent upon how exactly it is implemented. Since it is pretty clear that on A16 TSMC is not changing the std cell and just optionally “bolting” BS-TCN to the device TSMC will only get the potential utilization, perf, power improvements, and the resultant cost adder. Intel showed off in their implementation that they basically made the intel 3 210h but with a relaxed M0 to 36p which intel claims more than offset the cost adder while also giving the claimed P—P and utilization improvements. If Samsung is quoting 17% it is certainly possible they did something different than TSMC and intel and either didn’t relax M0 as much as intel or even at all like TSMC. Simultaneously if they reduced the M0 track count, there would be a guaranteed density improvement in addition to the utilization increase. But that is also contingent on the M0 being the limiter to SF2 cell size and not the FEOL (which is obviously unknown to me). It would also be really interesting if they used a different implementation than intel or TSMC (although I suspect EDA guys would want to throttle me for saying that ).

 

[IanD]

The density story is highly dependent upon how exactly it is implemented. Since it is pretty clear that on A16 TSMC is not changing the std cell and just optionally “bolting” BS-TCN to the device TSMC will only get the potential utilization, perf, power improvements, and the resultant cost adder. Intel showed off in their implementation that they basically made the intel 3 210h but with a relaxed M0 to 36p which intel claims more than offset the cost adder while also giving the claimed P—P and utilization improvements. If Samsung is quoting 17% it is certainly possible they did something different than TSMC and intel and either didn’t relax M0 as much as intel or even at all like TSMC. Simultaneously if they reduced the M0 track count, there would be a guaranteed density improvement in addition to the utilization increase. But that is also contingent on the M0 being the limiter to SF2 cell size and not the FEOL (which is obviously unknown to me). It would also be really interesting if they used a different implementation than intel or TSMC (although I suspect EDA guys would want to throttle me for saying that ).

All true, but since the area gain for BSPD is mainly because of removing the topside power grid and shortening each row of cells (and therefore interconnect length, which is where the power/speed improvement mainly comes from) it's obvious that the area saving depends on how dense the grid was, regardless of what else you do.

Looking inside the cell layouts -- both analogue and digital -- TSMC have already done a lot of area optimization for N2 in terms of cell height/width and balancing the various metal pitches and how they fit in with the nanosheet transistors, it's not obvious that removing the topside power grid allows anything radically new to be done in addition in A16.

The N2/A16 nanosheet transistors basically give an improvement in density -- more drive current in a given area -- to match the areas shrink from N3, but the fundamental performance (Ft, Fmax, gm/C) is similar -- actually a bit worse in some areas, the PMOS are noticeably slower, and self-heating is worse especially for the NMOS -- PMOS was bad in N3 anyway because the SiGe fins are poorer thermal conductors, nanosheet has made the problem worse... :-(