Running a foundry of Cash Cows and Little Fish: TSMC and the role of chiplets

[user nl]

During the last year many discussions on this SemiWiki website centered on the reasons why Intel started struggling versus the success of TSMC.

Many topics were discussed, like the IDM model versus Pure Play Foundry and the role of incompetent management, boards and financial engineering.

I'm not a semi expert and I may have missed quite some discussions about this topic, so perhaps people can share their opinion of another change during the years 2017-2022: the development of chiplets/tiles for leading edge logic.

I'm amazed at how the 7nm and 5 nm nodes of TSMC have evolved into enormous cash cows during the last 2-3 years as TSMC uses an aggressive 5-year depreciation of their tools, so that their gross margins of certain nodes rises to 65-75%?

This Table is what Gemini produced in some detailed discussions about estimated gross margins of TSMC's nodes in 2025 with fixed gross margins for the N7 and mature nodes, to re-produce the overall gross margins of TSMC as reported in each quarter of 2025. I have no insight in this matter, so please correct me if you think some GM's do not make sense.

The strong contribution of some super-high margin nodes (5nm and 7nm) and their role as the producers of many little fish/chiplets in leading edge semi for HPC, AI, mobile, laptops etc seems to suggest that these older nodes will have a much longer lifetime and high-profitable role as huge cash cows for TSMC.

So my question to this community: what may have been the effect of the chiplet-revolution in semi-manufacturing on the success of TSMC?

 

[hist78]

I'm amazed at how the 7nm and 5 nm nodes of TSMC have evolved into enormous cash cows during the last 2-3 years as TSMC uses an aggressive 5-year depreciation of their tools, so that their gross margins of certain nodes rises to 65-75%?

TSMC’s 5‑year depreciation schedule for fab equipment is neither aggressive nor unusual. It’s standard industrial practice and aligns with tax reporting requirements. For a leading edge foundry like TSMC, even a 3‑ to 5‑year horizon can bring enormous technological, market, and geopolitical changes. Recovering costs as quickly as tax law allows is simply prudent. Over the past five years, the pace of change has been so dramatic that very few companies could have predicted it accurately, let alone forecast the right products and capacity to capture shifting demand. A longer depreciation schedule, such as Intel’s 8‑year approach, exposes a company to unnecessary and avoidable risk.

Starting in January 2023, after using a 5‑year depreciation schedule for many years, Intel extended its depreciation period to 8 years. Because depreciation is a non‑cash expense, this change allowed Intel to reduce reported expenses and boost its accounting profits without using any cash. Or, in Intel’s case, it effectively reduced (duct taped) the size of its reported losses. In reality, this change does nothing to improve Intel’s competitiveness; it is purely an exercise in financial engineering.

For 2023, Intel reported GAAP net income of $1.7 billion. In my view, without extending the depreciation schedule, Intel likely would have reported a loss of $800 million, at least, instead.


"Effective January 2023, Intel increased the estimated useful life of certain production machinery and equipment from five years to eight years. When compared to the estimated useful life in place as of the end of 2022, Intel estimates total depreciation expense in 2023 was reduced by $4.2 billion. Intel estimates this change resulted in an approximately $2.5 billion increase to gross margin, a $400 million decrease in R&D expenses and a $1.3 billion decrease in ending inventory values."

Source: https://www.sec.gov/Archives/edgar/data/50863/000005086324000008/q423_earningsrelease.htm#:~:text=Effective January 2023, Intel increased,was reduced by $4.2 billion.

 

[user nl]

TSMC’s 5‑year depreciation schedule for fab equipment is neither aggressive nor unusual. It’s standard industrial practice and aligns with tax reporting requirements. For a leading edge foundry like TSMC, even a 3‑ to 5‑year horizon can bring enormous technological, market, and geopolitical changes. Recovering costs as quickly as tax law allows is simply prudent. Over the past five years, the pace of change has been so dramatic that very few companies could have predicted it accurately, let alone forecast the right products and capacity to capture shifting demand. A longer depreciation schedule, such as Intel’s 8‑year approach, exposes a company to unnecessary and avoidable risk.

Starting in January 2023, after using a 5‑year depreciation schedule for many years, Intel extended its depreciation period to 8 years. Because depreciation is a non‑cash expense, this change allowed Intel to reduce reported expenses and boost its accounting profits without using any cash. Or, in Intel’s case, it effectively reduced (duct taped) the size of its reported losses. In reality, this change does nothing to improve Intel’s competitiveness; it is purely an exercise in financial engineering.

For 2023, Intel reported GAAP net income of $1.7 billion. In my view, without extending the depreciation schedule, Intel likely would have reported a loss of $800 million, at least, instead.


"Effective January 2023, Intel increased the estimated useful life of certain production machinery and equipment from five years to eight years. When compared to the estimated useful life in place as of the end of 2022, Intel estimates total depreciation expense in 2023 was reduced by $4.2 billion. Intel estimates this change resulted in an approximately $2.5 billion increase to gross margin, a $400 million decrease in R&D expenses and a $1.3 billion decrease in ending inventory values."

Source: https://www.sec.gov/Archives/edgar/data/50863/000005086324000008/q423_earningsrelease.htm#:~:text=Effective January 2023, Intel increased,was reduced by $4.2 billion.

Yes, I understand the accounting trick of INTEL as some further "financial engineering", perhaps to try to keep their co-investors in their "SMART" capital coinvestment program "happy"?
https://ir.apollo.com/news-events/p...-and-apollo-agree-to-joint-venture-related-to

My question is more: does the chiplet development more actively lock the older nodes (like 5 nm and 7 nm) to the leading edge nodes 2nm and 3 nm? Such that they receive a much higher utilization, all these nodes get more connected, as the customers choose the best cost structure / performance ratio for their different tiles.

So do the chiplets provide a meaningful extra load of the 5 and 7 nm fabs?

 

[user nl]

OK a short followup:

I asked Gemini this question on what he estimates is the N5 capacity that TSMC uses for tiles (for N2/N3 products) and he comes up with a fraction of 28% of N5 wafer starts as of Jan 2026.

I asked how he calculates/knows that and then he provides a very detailed calculation. See attached pdf.

Does that sounds reasonable? Is Gemini so good in answering this with a reasonable accuracy?

 

[Xebec]

My question is more: does the chiplet development more actively lock the older nodes (like 5 nm and 7 nm) to the leading edge nodes 2nm and 3 nm? Such that they receive a much higher utilization, all these nodes get more connected, as the customers choose the best cost structure / performance ratio for their different tiles.

Based on products selling today -- the answer seems to be 'generally yes', but not always.

AMD's leading edge CPU chiplet products on N4 also use large N6 (7nm class) I/O dies. Their 2nm and 3nm next gen products (Zen 6) are also likely to use something from the 5nm (or maybe 7nm) class I/O and/or NPU dies. AMD Radeon is a mix - monolithic on N4, but also chiplet based products spanning N4/N5/N6.

Intel's Arrow Lake and Lunar Lake have N3B, N5P, and N6 chiplets. Panther Lake is brand new and uses a combo of Intel 18A and TSMC N3, and will be in production when others are using N2 for their base, so that starts to pull N3 into "trailing support node" (N-1) territory.

Both Intel and AMD also opportunitistically use N5/N7 class nodes for other monolithic products for cost and capacity reasons. Chipsets, lower end GPUs, networking products, etc.

However, Nvidia and Apple are generally sticking with monolithic on the latest node for their highest end products, while using "older" nodes for some lower end/older stuff. (Note that Nvidia's super large die sizes tend to mean N-1 or even N-2 soon, while Apple's smaller dice allow current "N" class products).

So in summary - there is tying of older nodes to the latest nodes to support chiplet architectures, but there's also just general demand for cost and capacity reasons, especially as new nodes don't improve upon older nodes quickly enough to justify "throwing out the old" immediately.

 

[user nl]

Here a graph generated by Gemini of the node lifetime cycles, where each node is normalized to the peak of their relative contribution to the overall revenue of TSMC in that specific year.
Interesting that during 15 years, for all these nodes the peak is around 30-35%. That seems a TSMC-law of business efficiency somehow?

The 5 nm rises more slowly because of various reasons (among them Covid) but is also predicted by Gemini to obtain the largest Area Under the Curve, so potentially make the 5/4 nm node the most valuable node for TSMC so far. Its peak was around 36% of total revenue.
That large potential AUC of the 5 nm curve is perhaps also (patially) the effect of the chiplet revolution these years?

Because the 2 nm is ramping and totally sold out for the coming 2 years Gemini predicts that 3 nm is near its peak of around 30% of total revenue. We'll find out.

It seems 7 nm is/will be partially cannibalized by TSMC into more advanced packaging capacity, as the fast rise of the chiplet technology needs a lot of advanced packaging capacity.

Of course, some big companies like NVIDIA, Apple, Microsoft etc may/will move some (small) orders the coming years to Intel Foundry (because of capacity and political reasons), but it is hard to believe that Intel Foundry will ever reach gross margins of 50-60%, simply because of the low volumes relative to TSMC that they process.

So my question: is the chiplet revolution in combination with the advanced packaging and the huge capacity that TSMC is building up these years also making them more of "a winner takes all" foundry for the coming decade?

 

[Paul2]

The need to find something to occupy the older, but still very expensive per-wafer nodes was the reason they pushed for multi-die integration so hard. It was foreseen that most of the industry would stop following the node race, so they had to find ways to keep wet nodes occupied post peak despite commodity silicon not coming to <40nm, thus aggressive promotion of the chiplet concept, and luring big name clients to it, to make the industry to follow.

 

[hist78]

Yes, I understand the accounting trick of INTEL as some further "financial engineering", perhaps to try to keep their co-investors in their "SMART" capital coinvestment program "happy"?
https://ir.apollo.com/news-events/p...-and-apollo-agree-to-joint-venture-related-to

My question is more: does the chiplet development more actively lock the older nodes (like 5 nm and 7 nm) to the leading edge nodes 2nm and 3 nm? Such that they receive a much higher utilization, all these nodes get more connected, as the customers choose the best cost structure / performance ratio for their different tiles.

So do the chiplets provide a meaningful extra load of the 5 and 7 nm fabs?

TSMC does move equipment (or space) from mature nodes to advanced packaging. However, they do not move leading edge node equipment into advanced packaging because those tools remain extremely profitable and in high demand. Chiplets help generate additional volume on older nodes, not necessarily only mature nodes, but that alone is not sufficient. TSMC must maintain high gross and net profit margins across all nodes.

From the pie charts below, we can see that up to 2024, TSMC still derived 31% or more of its revenue from nodes older than 7nm. In 2025, TSMC attributed 26% of its revenue to mature nodes (those older than 7nm). 26% of TSMC’s 2025 revenue of US$122.42 billion is US$31.83 billion, likely larger than the combined 2025 revenue of Samsung Foundry, SMIC, and UMC. Because such a large portion of revenue comes from mature nodes, TSMC must maintain strong profitability on both mature and leading edge technologies in order to achieve overall high profit margins.

I believe TSMC uses several approaches to achieve this:

1. 1. Continuous investment and R&D in selected mature nodes to improve efficiency, reduce cost, and expand capabilities for specialty applications such as automotive, industrial, and IoT.
2. 
   
3. 2. Migrating or reusing equipment from older nodes to newer ones whenever possible, such as moving some tools from 7nm/5nm to help 3nm production. This is not easy and requires significant foresight in design and long term planning.
4. 
   
5. 3. Strict financial discipline. For example, assume a similar process node has four years of peak demand and high margins for both TSMC and Intel Foundry. Currently TSMC uses a five‑year depreciation schedule, while Intel uses eight years. TSMC aims to recover most of its capital investment during the four high‑demand years when pricing is strongest. Intel, on the other hand, must continue carrying the same tools for three additional years (8–5=3) when demand and pricing have already declined.

This dynamic pushes TSMC to be more cost conscious and operationally efficient. It influences how TSMC selects customers and partners, sets pricing, and chooses its technology roadmap.

 

[user nl]

Because such a large portion of revenue comes from mature nodes, TSMC must maintain strong profitability on both mature and leading edge technologies in order to achieve overall high profit margins.


View attachment 4130

I was rereading the remarks of CFO at the Q4-2025 reporting and noticed:

"We have just guided our first quarter gross margin to increase by 170 basis points to 64% at the midpoint primarily driven by continued cost improvement effort including productivity gains and a higher overall capacity utilization rate partially offset by continued dilution from our overseas fabs. Looking at full year 2026, given the six factors, there are a few puts and takes I would like to share. On the one hand, we expect our overall utilization rate to moderately increase in 2026. N3 gross margin is expected to cross over to the corporate average sometime in 2026 and we continue to work hard to earn our value. In addition, we are leveraging our manufacturing excellence to drive greater productivity in our fabs to generate more wafer output. We are also increasing across node capacity optimization which includes flexible capacity support among N7, N5 and N3 nodes to support our profitability."


Suppose that the full year gross margin is similar to the Q1-2026 margin of guided 64%, it means that TSMC has managed to get the gross margin of N3 in very short time (~2.5-3 years) already to some 64%.
Gemini estimated N3 gross margin of around 54% in Q4-2025, so those estimated GM values by Gemini may be quite reasonable?

N3 and N5 are now both enormous cashcows, with N5 perhaps growing to 70-75 gross margin in 2026?

Will Intel FS ever have gross margins for their leading edge nodes of >50% ??


https://www.investing.com/news/tran...-2025-results-show-strong-growth-93CH-4448708

 

[Xebec]

I was rereading the remarks of CFO at the Q4-2025 reporting and noticed:

"We have just guided our first quarter gross margin to increase by 170 basis points to 64% at the midpoint primarily driven by continued cost improvement effort including productivity gains and a higher overall capacity utilization rate partially offset by continued dilution from our overseas fabs.

I do not doubt at all that TSMC is doing a lot of work to keep their nodes cost efficient and extremely productive. But they also aren't going to "broadcast" that their margins have gone up because they're charging more for newer nodes (where they are peerless) vs. previous nodes (that had competition).

I'm all for business making money -- that's why business exists, but I'm also curious how much of TSMC's margin is going up due to being the near-monopoly on leading edge vs. engineering efficiency. That said, there is an upper limit on what pricing the market will accept, even in a monopoly situation.

 

[user nl]

I do not doubt at all that TSMC is doing a lot of work to keep their nodes cost efficient and extremely productive. But they also aren't going to "broadcast" that their margins have gone up because they're charging more for newer nodes (where they are peerless) vs. previous nodes (that had competition).

I'm all for business making money -- that's why business exists, but I'm also curious how much of TSMC's margin is going up due to being the near-monopoly on leading edge vs. engineering efficiency. That said, there is an upper limit on what pricing the market will accept, even in a monopoly situation.

Perhaps TSMC got inspired by NVIDIA's gross margins during 2023-2025 and that their CEO stated in public that he thought that TSMC could charge more for their leading edge nodes as they delivered such great value

NVIDIA had 70-75 gross margins, so no need for TSMC to be so modest to keep their gross margins around 53-56%, I think in 2026 and 2027 they will try to move to 60-65%, and at the same time keep capex investments of some 30-35% of their revenue (in 2026 estimated 54/160 = 34%).

Yes, the finances of TSMC as a quasi monopolist at global scale are just staggering. They know how to build fabs of 20-30 B$, how to run them the most efficiently and do this at an immense scale. That immense scale seems to provide TSMC at least a 30% higher gross margin than INTEL Foundry will ever see around 2030 (Intel's Foundry GM target seems to be around 30% at that time).

I have no detailed insight in how effciently TSMC runs a fab of 30-40 kwspm, but the fact that they now run a virtual global fab of 7nm, 5nm, 3nm and 2 nm nodes with simply staggering wafer starts must give them unprecidented value of scale running all these different chip designs at huge capacity, effectively getting all systematic defects in design and tools down so quickly. They have diversity of designs/IP and huge wspm numbers, the best of both worlds for a fabless customer.

These are some numbers of leading edge wafers at the end of 2025 (total 530 kwspm) and estimate at the end of 2027 (690 kwspm):