Revisiting how many EUV wafers per day

[Fred Chen]

ASML had projected that 1 EUV tool per layer supports 45,000 wafers per month: https://www.anandtech.com/show/13904/asml-to-ship-30-euv-scanners-in-2019

At this point, Samsung and TSMC each have somewhere around 30 EUV tools. The targeted wafers per month for Samsung this year is 150,000 wafers per month (30/(150/45) = 9 layers?): https://www.kitguru.net/channel/gen...y-set-to-double-tsmc-7nm-wafer-order-in-2020/ while TSMC 5nm is projected to be 60,000 wafers per month (30/(60/45) = 22-23 layers?): https://semiengineering.com/5nm-vs-3nm/

Samsung using EUV on 9 layers sounds about right, which indicates each tool can be running 1500 wafers per day on its layer to meet 45,000 wafers per month. TSMC 5nm is said to be 15 layers instead of 22, suggesting that the wafers per day per tool might still be 1000 instead of 1500. It's also possible some layers require two passes through the same tool. 1000-1500 wafers per day is actually very low (40-63 WPH, compared to >250 WPH for immersion) so this is also taken to be an effective throughput. That is, it is more a measure of how available the tool is for operation.

The key reason is the EUV tools get incredibly dirty. The EUV light collector suffers from tin deposition, which needs a few days downtime every couple of weeks to remove. And the masks themselves need to be dry-cleaned after every 10,000 wafers. The time to expose a wafer also depends on how many field steps are used, as well as how high a dose is used. A higher dose is needed to reduce photon shot noise, and more, smaller field steps are needed to avoid slit curvature.

 

[Tanj]

" According to ASML, one EUV layer requires one EUV step-and-scan system for every ~45,000 wafer starts per month. "

A bit lower down you can see they project 10..20 layers needed in logic and 2..6 layers needed in memory. The Samsung numbers indicate 9 layers, the TSMC numbers indicate 22. Perhaps some of the 30 machines are older, perhaps some are used in experimental or pilot work. The TSMC numbers do seem a little slow (it seems unlikely they use 20 EUV layers), but not hugely.

 

[Fred Chen]

" According to ASML, one EUV layer requires one EUV step-and-scan system for every ~45,000 wafer starts per month. "

A bit lower down you can see they project 10..20 layers needed in logic and 2..6 layers needed in memory. The Samsung numbers indicate 9 layers, the TSMC numbers indicate 22. Perhaps some of the 30 machines are older, perhaps some are used in experimental or pilot work. The TSMC numbers do seem a little slow (it seems unlikely they use 20 EUV layers), but not hugely.

I was about to go back to change my original post to reflect the layer count. After this post, it should be updated.

Samsung is likely 9 layers (I had estimated 63 vs 90 masks for 7nm with vs. w/o EUV). The difference of 27 could be 9 layers x 3 masks each. The single exposure replaces four.

TSMC 5nm was said to be 15 layers (instead of 22). Maybe some of them are multiple-exposed if the wafers per day is kept the same. Memory shouldn't require any layers (actually EUV doesn't help).

 

[Fred Chen]

" According to ASML, one EUV layer requires one EUV step-and-scan system for every ~45,000 wafer starts per month. "

A bit lower down you can see they project 10..20 layers needed in logic and 2..6 layers needed in memory. The Samsung numbers indicate 9 layers, the TSMC numbers indicate 22. Perhaps some of the 30 machines are older, perhaps some are used in experimental or pilot work. The TSMC numbers do seem a little slow (it seems unlikely they use 20 EUV layers), but not hugely.

For reference, immersion tools each run 4000-6000 wafers per day (120,000-180,000 wafers per month). So these still need to be kept sufficiently available for the leading edge. Recent purchases from ASML show this priority:

Since the immersion tools are 4x faster than EUV tools, as long as fewer than 4 passes through an immersion tool are required, it is cheaper to use the immersion tools to get the same number of wafers per month.

 

[hskuo]

ASML had projected that 1 EUV tool per layer supports 45,000 wafers per month: https://www.anandtech.com/show/13904/asml-to-ship-30-euv-scanners-in-2019

At this point, Samsung and TSMC each have somewhere around 30 EUV tools. The targeted wafers per month for Samsung this year is 150,000 wafers per month (30/(150/45) = 9 layers?): https://www.kitguru.net/channel/gen...y-set-to-double-tsmc-7nm-wafer-order-in-2020/ while TSMC 5nm is projected to be 60,000 wafers per month (30/(60/45) = 22-23 layers?): https://semiengineering.com/5nm-vs-3nm/

Samsung using EUV on 9 layers sounds about right, which indicates each tool can be running 1500 wafers per day on its layer to meet 45,000 wafers per month. TSMC 5nm is said to be 15 layers instead of 22, suggesting that the wafers per day per tool might still be 1000 instead of 1500. It's also possible some layers require two passes through the same tool. 1000-1500 wafers per day is actually very low (40-63 WPH, compared to >250 WPH for immersion) so this is also taken to be an effective throughput. That is, it is more a measure of how available the tool is for operation.

The key reason is the EUV tools get incredibly dirty. The EUV light collector suffers from tin deposition, which needs a few days downtime every couple of weeks to remove. And the masks themselves need to be dry-cleaned after every 10,000 wafers. The time to expose a wafer also depends on how many field steps are used, as well as how high a dose is used. A higher dose is needed to reduce photon shot noise, and more, smaller field steps are needed to avoid slit curvature.

You might need to check your assumptions about EUV tool number and capacity in Samsung and TSM. It might be concluded totally wrong. If Samsung logic EUV fab will build 150kwpm by 2020, what revenue it will contribute? Be careful.

 

[Fred Chen]

It's true there are assumptions based on others' reports and my own estimate of 30 tools each for Samsung and TSMC is not precise; we know there are 57 NXE:3400, so the total actually used by each is less than 30. I am not sure if pre-NXE:3400 can be included. Also a few NXE:3400 went to GlobalFoundries and Intel. The only cross-check I can offer is from the recent graph we referred to below:

The wafers per day estimated from this graph visually (again, not that precise, but best effort) is 5.5 million wafers in the last quarter, assuming 55 tools, giving 5,500,000/55/90 = 1111 wafers/day per tool, which is in the 1000-1500 wafer per day range, and toward the low side. If 1000 wpd is more believable than 1500 wpd, then if still keeping the 9 layer count and 30 tools for Samsung, 150 kpwm should be revised down to 100 kwpm. If we adjust tool count down to 24, then down to 80 kwpm.

The Samsung 150 kwpm was reported in the source article and here as a target, so the actual likely falls short, maybe far short, although just searching now again, can't find that number for recent times.

Note: just noticed after accounting for ~82% availability, the wafers per day is still <1500!

 

[hskuo]

It's true there are assumptions based on others' reports and my own estimate of 30 tools each for Samsung and TSMC is not precise; we know there are 57 NXE:3400, so the total actually used by each is less than 30. I am not sure if pre-NXE:3400 can be included. Also a few NXE:3400 went to GlobalFoundries and Intel. The only cross-check I can offer is from the recent graph we referred to below:
View attachment 216
The wafers per day estimated from this graph visually (again, not that precise, but best effort) is 5.5 million wafers in the last quarter, assuming 55 tools, giving 5,500,000/55/90 = 1111 wafers/day per tool, which is in the 1000-1500 wafer per day range, and toward the low side. If 1000 wpd is more believable than 1500 wpd, then if still keeping the 9 layer count and 30 tools for Samsung, 150 kpwm should be revised down to 100 kwpm. If we adjust tool count down to 24, then down to 80 kwpm.

The Samsung 150 kwpm was reported in the source article and here as a target, so the actual likely falls short, maybe far short, although just searching now again, can't find that number for recent times.

Note: just noticed after accounting for ~82% availability, the wafers per day is still <1500!

Some inputs: 1. GF's EUV tools had been bought back by ASML for a while.
2. Intel used to put order of 15 EUV tools ~ 4~5 years ago
3. From estimation, Samsung's logic EUV capacity will be no more than 40kwspm by 2020

 

[Fred Chen]

Some inputs: 1. GF's EUV tools had been bought back by ASML for a while.
2. Intel used to put order of 15 EUV tools ~ 4~5 years ago
3. From estimation, Samsung's logic EUV capacity will be no more than 40kwspm by 2020

Thanks for the inputs. I remember the Intel order and wondered what happened to GF's tools once they stopped 7nm. The Samsung estimate is plausible, could you give some references? Thanks again.

 

[jmlobert]

Memory shouldn't require any layers (actually EUV doesn't help).

Can you please explain why you think EUV doesn't help with memory?

Samsung Announces Industry’s First EUV DRAM with Shipment of First Million Modules

EUV-based 1st-gen 10nm-class DRAM (D1x) has completed its customer evaluations; EUV to be fully deployed from 4th-gen 10nm-class DRAM (D1a) next year

news.samsung.com

 

[Fred Chen]

Can you please explain why you think EUV doesn't help with memory?

Samsung Announces Industry’s First EUV DRAM with Shipment of First Million Modules

EUV-based 1st-gen 10nm-class DRAM (D1x) has completed its customer evaluations; EUV to be fully deployed from 4th-gen 10nm-class DRAM (D1a) next year

news.samsung.com

For DRAM, EUV must use very directed illumination, so it cannot use the full 26 mm exposure field but maybe a few mm (due to rotation). Thus, more exposure steps are needed. Additionally some layers have been arranged hexagonally (Samsung has also demonstrated this such as below), which also do not involve multiple exposures on non-EUV tools. In other words, there is no productivity advantage, as non-EUV tools can use the full 26 mm.

The illumination is also not balanced, with larger angles weaker than smaller angles, which leads to shifts with defocus. Actually, Samsung pointed out this issue in their 1997 SPIE paper, "Pattern Deformation Induced from Intensity-Unbalanced Off-Axis Illumination."