Question to Mr. Chen: stacked SRAM/RAM/FLASH in MCUs

[Paul2]

What you think? Can we see memory stacking in something as cheap as MCUs?

The reason I am asking, is that I can't recall the last time we shipped an MCU product without PSRAM. Almost everything with complex programming gets firmwares exceeding SRAM sizes of most beefy MCUs.

Given this, I see some people questioning the rationale of packing MCUs with a lot of very expensive per area SRAM (especially for 90nm-180nm products,) when people run out of it anyways.

 

[Paul2]

@Fred Chen

 

[Fred Chen]

Sorry I missed your question.

Perhaps a good starting point for consideration is the capacity. If it's low enough density, like MB, staying on-die is expected. Stacking definitely comes into consideration with GB of RAM.

If you have a 0.04 um2 cell size, that's 0.04 mm2 for Mb, 40 mm2 for Gb.

Afterthought: some other area is needed for circuitry to control this memory. For larger memory, it could require a larger controller. Case in point: http://www.skyhighmemory.com/download/1-s2.0-S002627141930633X-main.pdf

 

[Paul2]

Sorry I missed your question.

Perhaps a good starting point for consideration is the capacity. If it's low enough density, like MB, staying on-die is expected. Stacking definitely comes into consideration with GB of RAM.

If you have a 0.04 um2 cell size, that's 0.04 mm2 for Mb, 40 mm2 for Gb.

Afterthought: some other area is needed for circuitry to control this memory. For larger memory, it could require a larger controller. Case in point: http://www.skyhighmemory.com/download/1-s2.0-S002627141930633X-main.pdf

I've seen some firmwares eating up to 16MB of PSRAM loaded with code to talk to Amazon, or AzureIoT, and some were managing to hit OOM even with that.

We probably don't talk about 180nm MCUs, but there are still tons of 90nm mainstream MCUs with STM32 being the biggest family. That should be 1.2-1.5 square microns for more power efficient 6T designs. Putting even 4MB SRAM on a 90nm die is out of question.

Most MCUs use PSRAM, some smart ones have fancy serial connection for Winbond style MCU rams, but basic expectation is that the memory follows synchronous access pattern.

So, I think we talk about either co-packaging one die of fast PSRAM, or actual SRAM.