Physical limits from theoretical physics perspective

[melkord]

Hi,


In the source that I came across, it is mentioned that the physical limit from theoretical physics perspective for binary logic devices is 1 x 3 nm^2.
With the insulation circumferences the device, 1 device ends up taking 2 x 4 nm^2.

So far, the discussion about device scaling limitation that I found is mostly from the Lithography perspective.
let's say, we are able to overcome the lithography challenges to fabricate the device and delay the end of Moore's Law for a few technological nodes.

my questions:

1. between current state of the art technology (Lithography limitation) and that physical limits from theoretical physics, how much room do we still have actually?

2. Has this limit ever been discussed in the international conferences like IEDM, IMEC yearly meeting, etc? If yes, what are their opinion about a conclusion/prediction like that?



source
paper

https://ieeexplore.ieee.org/document/4567291

the same author also wrote a chapter in a book.

https://www.springer.com/in/book/9789048193783

 

[Tanj]

Realize that those dimensions are far, far smaller than current devices. A 7nm device for example might be 2 fins and 2 or three gates orthogonal, where a 7nm process does not mean any part of that is 7nm. A single fin might be that wide but the distance between fins is more like 35. If you look around this site you can find threads discussing design rules and showing some of the device layouts.

Some elements that you mention are proven, for example insulating layers on the order of 1nm thick do exist. But nothing even close to a 4nm sq device currently exists. More like 100x that area in practice. If that really is our limit, we should celebrate.

The practical limits for devices that small are likely to be things like poor ratio between off and on. In theory that works, but in practice you cannot build a big chip if devices leak too much when off. The billions of devices on a chip are mostly inactive at any given moment and current designs depend on that. You could design FINfet devices much smaller then used in practice but you would then have leaky devices with poor drive ratios. It is not all about the quantum limits of being on or off, it is more about building a library of practical devices.