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I want to design a password protection circuit to enable the functionality of IC.
Input can be given from 4*4 keypad.
When password is entered from keypad then and then only IC should be functional.
I need to design it in transistor level.
So what are the blocks required for the designing of this chip???
Your requirement can be addressed by a method where a state machines in a design will behave as needed only if you apply a sequence (here password) to the inputs. Otherwise it will behave arbitrarily and will not work. The process is very effective with very minimal overhead of area and power
Yes, assuming you are not trying to protect against the many physical attacks someone could throw at it, you would have a state machine, likely all in GO2 (IO V transistors) so you do not need POR and regulation up for this. It would match the pattern of the password (unclear if you are storing that password in metal layers or polyfuses or what, but you have to load it if not in metal). If found, it would be a term in your POR circuit to power up the processor. If you only care about operational effects, then it could be in GO1 (core transistors) and would hold the device in system reset until matched. You do need to consider how your model works for wafer test. Again, 1st step is decide how much you care about physical attack (side channel, decap and probe, using test modes to attack, SEM/XRAY scan for fuses, etc).
