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There's a good summary of opinions on what the 3D Xpoint memory could be here. Intel and Micron claim that their new memory is NOT ReRAM, not memristor. Some think that it is a Conductive Bridging RAM or CBRAM.
When the first products get introduced later this year, then we'll see which markets pick it up first. My guess is that they will first aim at replacing SSD.
I'm thinking that this memory will go to the ones who pay premium until production and trust is ramped up to ssd volumes. Its advantage is not in the density dimension, but rather the fast and non complex writing afaik. Depending on price, it could replace SRAM I guess.
Does anyone know what interface this memory will run at? Personally I'd like to see high speed random word-access for SRAM competition.
Edit:Anyone know if this memory type does destructive reads?
Short summary of your specific questions:
- They are targeting a 2016 launch, both for the devices and for Xeon CPUs that can access them
- They could be available either in an SSD form factor (NVMe) or in a DIMM form factor (on the DDR4 bus)
- They are much faster than NAND, but about an order of magnitude longer latency than DRAM
- Nobody has definitively said what the technology is, but the Q&A gives some clues on what it's not
I'm thinking that this memory will go to the ones who pay premium until production and trust is ramped up to ssd volumes. Its advantage is not in the density dimension, but rather the fast and non complex writing afaik. Depending on price, it could replace SRAM I guess.
Does anyone know what interface this memory will run at? Personally I'd like to see high speed random word-access for SRAM competition.
Edit:Anyone know if this memory type does destructive reads?
SRAM is faster than DRAM, by a lot, and DRAM is faster than Xpoint. Of course, that's latency, and no interface is going to overcome that. Latency is the big problem, bandwidth can be overcome with more channels, which increase latency a little, so having low latency is really the key. Also, increasing bandwidth right now wouldn't improve CPU performance much at all, although certainly would help the GPU portion of it, if it has one.
I do not believe it has destructive reads, as nothing has indicated it does. Even the writes are supposed to have 1000x what NAND has. So, I think it's very, very unlikely it would have destructive reads.
It is said by Intel to be a change of the whole bulk material (not a part or component) between the electrodes, it looks like a new phase change material (not the original PCM). So it could be some time before we know enough about it. Retention is naturally a concern.
Cross-point architecture and the ability to stack is a big deal and will be around for a long time. I'd guess that New Memory B is just a different bitcell but still within a 3D cross-point array. Certainly lithography isn't going to change significantly by 2017, so maybe by then they will have worked out the bugs in PCM, but they (Numonyx) have been saying that for the last decade or so. Has anyone noticed Ed Doller (Numonyx CTO/Micron VP) is no longer with Micron since April?
The repeated crosspoint patterning should be shunned here just like the dreaded multiple patterning in the usual lithography sense. It might be even worse, given that each level requires (at least) double patterning (for 10-20 nm-class) and the density scales linearly with the number of patterning steps unlike the lithography sense where it is more nonlinear.
but aren't the alternatives that don't suffer from this constraint hampered by lack of bit level/byte level addressability? and therefore not a SCM candidate? What are the other options?
but aren't the alternatives that don't suffer from this constraint hampered by lack of bit level/byte level addressability? and therefore not a SCM candidate? What are the other options?
The 2D crosspoint is still attractive. Although not as scalable as 3D NAND, it offers the opportunity to avoid periphery area outside the array. Actually the periphery area grows as a function of number of vertical layers. If there is low area efficiency of the array, then Gb/mm2 would saturate. If the periphery dominates cost AND there is good area efficiency, then there is some room to stack 2D crosspoint into 3D before the periphery area exceeds the array area. On the other hand, with the periphery being mature technology and the layer-stacking technology/materials being new, it is probably difficult to readily achieve cost reduction even with good area efficiency, until the materials mature.
Two years after first announcing 3D Xpoint, Intel finally has a product using this technology, so let's see if the industry drives high volumes or not:
Two years after first announcing 3D Xpoint, Intel finally has a product using this technology, so let's see if the industry drives high volumes or not:
If I read it correctly, Optane is volatile so it can't be used as storage? Then why even have the SSD? Hard to believe it has the endurance let alone speed of volatile RAM, which should not be microsecond range.
If I read it correctly, Optane is volatile so it can't be used as storage? Then why even have the SSD? Hard to believe it has the endurance let alone speed of volatile RAM, which should not be microsecond range.
Samsung is touting its Z-SSD, directed against 3D Xpoint. It would be higher capacity and likely better retention, while probably not losing badly in other areas. It is said to be based on its highly successful 3D-NAND technology.