Daniel Payne
Moderator
I attended the MunEDA User Group Meeting in November, and now you can view all of the customer presentations about recent developments in low power/low noise full custom circuit design, fast design migration, efficient and safe statistical circuit analysis for parametric variation and yield, and high performance full custom circuit design in advanced process nodes with FinFET and FDSOI.
[table]
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| valign="middle" | Download the full conference Proceedings (87 MB)
|-
| valign="middle" | [table]
|-
| colspan="3" valign="middle" | Technical Session D1.1: Opening & What's new
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| rowspan="2" valign="middle" |
| valign="middle" | STMicroelectronics - MUGM 2014 Chair Opening Remarks
P. Daglio
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | MunEDA - What's new in WiCkeD 6.7 - Integration & R&D Roadmap
F. Schenkel
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | MunEDA - WiCkeD 6.7 Tool Demo - Enhancements & New Features
M. Yakupov
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | ICScape - Accelerate Design Closure
J. Xing M. Qin Y.Han
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
|-
| colspan="3" valign="middle" | Technical Session D1.2: Robustness Verification and Sign-off for RF Design and Data Converters
|-
| rowspan="2" valign="middle" |
| valign="middle" | MunEDA - Statistical Verification and Analysis Tools
M. Pronath
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | SMIC - Process related yield debug and optimization of analog IP with MunEDA WiCKeD
C. Zhu
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | Lantiq - Sign-off Flow for RF Applications with WiCkeD in a 65nm Technology
D. Diaz-Lopez G. Guruvaiah B. Lemaitre P. Pessl
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
|-
| rowspan="2" valign="middle" |
| valign="middle" | Novatek - S&H Sample & Hold (ADC) Mismatch Analysis and Sizing using WiCkeD
J. Chu
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | IPGEN - New layout generation techniques for variation sensitive analog circuits
R. Wittmann
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
|-
| colspan="3" valign="middle" | Technical Session D1.3: Aging and Reliability
|-
| rowspan="2" valign="middle" |
| valign="middle" | MunEDA - Reliability & Robustness Based Design Using WiCkeD (Presentation & Tool-Demo)
C. Roma
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | STMicroelectronics - I/O Design Optimization Flow for Reliability In Advanced CMOS Nodes
F. Cacho V. Huard
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | Infineon - Reliability Aware Design of Relaxation Oscillator in Advanced CMOS Technology Nodes with WiCkeD
W. Wang G. Georgakos G. Rott W. Gustin
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | STMicroelectronics - IOs circuit optimization activities to enhance productivity, circuit robustness and improve existing reliability flow
A. Aggarwal
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| colspan="3" valign="middle" | Technical Session D2.1: Cell libraries and custom digital blocks
|-
| rowspan="2" valign="middle" |
| valign="middle" | Sapienza University Rome - Digital standard cell noise margin optimization, also considering aging effects with MunEDA WiCkeD and Synopsys MOSRA tools (MANON)
M. Olivieri Z. Abbas
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
|-
| rowspan="2" valign="middle" |
| valign="middle" | Infineon - Safeguarding Holdtime Margin for Internal Scan Chain in Multibit-Register Standardcells
A. Lang A. Huber
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | Altera - Distributed Memory Design (MLAB) - design optimization and worst case analysis on memory cells, datapaths and write pulse generators with WiCkeD
G.H. Oh G.M. Chan
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| colspan="3" valign="middle" | Technical Session D2.2: Full Custom Design Migration
|-
| rowspan="2" valign="middle" |
| valign="middle" | MunEDA - Advances in Circuit Migration (Tutorial)
M. Pronath
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | HLMC - 55nm to 40nm Bandgap porting with SPT & High gain Amp optimization with MunEDA WiCkeD
L. Ye Y. Shan
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | Fraunhofer - Silicon Proof of the Intelligent Analog IP Design Flow using WiCkeD
B. Prautsch
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
|-
| rowspan="2" valign="middle" |
| valign="middle" | MunEDA - Full-Custom Low Power Design Methodology with MunEDA WiCkeD
M. Yakupov
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| colspan="3" valign="middle" | Technical Session D2.3: Robust Analog Design I
|-
| rowspan="2" valign="middle" |
| valign="middle" | MunEDA - Ultra High Sigma (6+ Sigma) Analysis - High Sigma is not enough (Tutorial)
V. Glöckel
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | STMicroelectronics - Corner Verification and Design Optimization in Smart Power & Non-Volatile Memory Technologies
E. Raciti P. Daglio
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | University Frankfurt - FEATS - explorative automated topology synthesis with WiCkeD
M. Meissner L. Hedrich
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
|-
| rowspan="2" valign="middle" |
| valign="middle" | Fraunhofer - Advanced measures for OpAmp optimization with WiCkeD
E. Herzer M. Oberst
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| colspan="3" valign="middle" | Technical Session D2.4: Robust Analog Design II
|-
| rowspan="2" valign="middle" |
| valign="middle" | STMicroelectronics - Design validation and development of RF macrocells
A. Capasso A. Colaci
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | ARP Microsystems - High-Voltage Automotive Analog IP Development for SOC using WiCkeD tools
A. Silaev A. Bratsun Y. Silaeva
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
|-
| rowspan="2" valign="middle" |
| valign="middle" | Altera - Full-custom and Semi-custom Clock Trees Optimization using MunEDA WiCkeD - Clock Skew Matching, Clock Insertion Delay and Duty-Cycle
B. Y. Ng
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | STMicroelectronics - SMAC - Smart components and Smart Systems integration (FP7-ICT-2011-7)
A. Ciccazzo
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
[/table]
|-
[/table]
[table]
|-
| valign="middle" | Download the full conference Proceedings (87 MB)
|-
| valign="middle" | [table]
|-
| colspan="3" valign="middle" | Technical Session D1.1: Opening & What's new
|-
| rowspan="2" valign="middle" |
| valign="middle" | STMicroelectronics - MUGM 2014 Chair Opening Remarks
P. Daglio
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | MunEDA - What's new in WiCkeD 6.7 - Integration & R&D Roadmap
F. Schenkel
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | MunEDA - WiCkeD 6.7 Tool Demo - Enhancements & New Features
M. Yakupov
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | ICScape - Accelerate Design Closure
J. Xing M. Qin Y.Han
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
|-
| colspan="3" valign="middle" | Technical Session D1.2: Robustness Verification and Sign-off for RF Design and Data Converters
|-
| rowspan="2" valign="middle" |
| valign="middle" | MunEDA - Statistical Verification and Analysis Tools
M. Pronath
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | SMIC - Process related yield debug and optimization of analog IP with MunEDA WiCKeD
C. Zhu
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | Lantiq - Sign-off Flow for RF Applications with WiCkeD in a 65nm Technology
D. Diaz-Lopez G. Guruvaiah B. Lemaitre P. Pessl
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
|-
| rowspan="2" valign="middle" |
| valign="middle" | Novatek - S&H Sample & Hold (ADC) Mismatch Analysis and Sizing using WiCkeD
J. Chu
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | IPGEN - New layout generation techniques for variation sensitive analog circuits
R. Wittmann
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
|-
| colspan="3" valign="middle" | Technical Session D1.3: Aging and Reliability
|-
| rowspan="2" valign="middle" |
| valign="middle" | MunEDA - Reliability & Robustness Based Design Using WiCkeD (Presentation & Tool-Demo)
C. Roma
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | STMicroelectronics - I/O Design Optimization Flow for Reliability In Advanced CMOS Nodes
F. Cacho V. Huard
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | Infineon - Reliability Aware Design of Relaxation Oscillator in Advanced CMOS Technology Nodes with WiCkeD
W. Wang G. Georgakos G. Rott W. Gustin
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | STMicroelectronics - IOs circuit optimization activities to enhance productivity, circuit robustness and improve existing reliability flow
A. Aggarwal
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| colspan="3" valign="middle" | Technical Session D2.1: Cell libraries and custom digital blocks
|-
| rowspan="2" valign="middle" |
| valign="middle" | Sapienza University Rome - Digital standard cell noise margin optimization, also considering aging effects with MunEDA WiCkeD and Synopsys MOSRA tools (MANON)
M. Olivieri Z. Abbas
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
|-
| rowspan="2" valign="middle" |
| valign="middle" | Infineon - Safeguarding Holdtime Margin for Internal Scan Chain in Multibit-Register Standardcells
A. Lang A. Huber
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | Altera - Distributed Memory Design (MLAB) - design optimization and worst case analysis on memory cells, datapaths and write pulse generators with WiCkeD
G.H. Oh G.M. Chan
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| colspan="3" valign="middle" | Technical Session D2.2: Full Custom Design Migration
|-
| rowspan="2" valign="middle" |
| valign="middle" | MunEDA - Advances in Circuit Migration (Tutorial)
M. Pronath
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | HLMC - 55nm to 40nm Bandgap porting with SPT & High gain Amp optimization with MunEDA WiCkeD
L. Ye Y. Shan
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | Fraunhofer - Silicon Proof of the Intelligent Analog IP Design Flow using WiCkeD
B. Prautsch
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
|-
| rowspan="2" valign="middle" |
| valign="middle" | MunEDA - Full-Custom Low Power Design Methodology with MunEDA WiCkeD
M. Yakupov
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| colspan="3" valign="middle" | Technical Session D2.3: Robust Analog Design I
|-
| rowspan="2" valign="middle" |
| valign="middle" | MunEDA - Ultra High Sigma (6+ Sigma) Analysis - High Sigma is not enough (Tutorial)
V. Glöckel
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | STMicroelectronics - Corner Verification and Design Optimization in Smart Power & Non-Volatile Memory Technologies
E. Raciti P. Daglio
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | University Frankfurt - FEATS - explorative automated topology synthesis with WiCkeD
M. Meissner L. Hedrich
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
|-
| rowspan="2" valign="middle" |
| valign="middle" | Fraunhofer - Advanced measures for OpAmp optimization with WiCkeD
E. Herzer M. Oberst
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| colspan="3" valign="middle" | Technical Session D2.4: Robust Analog Design II
|-
| rowspan="2" valign="middle" |
| valign="middle" | STMicroelectronics - Design validation and development of RF macrocells
A. Capasso A. Colaci
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | ARP Microsystems - High-Voltage Automotive Analog IP Development for SOC using WiCkeD tools
A. Silaev A. Bratsun Y. Silaeva
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
|-
| rowspan="2" valign="middle" |
| valign="middle" | Altera - Full-custom and Semi-custom Clock Trees Optimization using MunEDA WiCkeD - Clock Skew Matching, Clock Insertion Delay and Duty-Cycle
B. Y. Ng
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
| rowspan="2" valign="middle" |
| valign="middle" | STMicroelectronics - SMAC - Smart components and Smart Systems integration (FP7-ICT-2011-7)
A. Ciccazzo
| rowspan="2" valign="middle" |
|-
| valign="middle" | Download presentation as PDF document
View presentation with Adobe Presenter
|-
[/table]
|-
[/table]