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Why this 25-year-old technology may be the memory of choice for leading edge designs and in automotive applications.
semiengineering.com
Magneto-resistive RAM (MRAM) appears to be gaining traction at the most advanced nodes, in part because of recent improvements in the memory itself and in part because new markets require solutions for which MRAM may be uniquely qualified.
There are still plenty of skeptics when it comes to MRAM, and lots of potential competitors. That has limited MRAM to a niche role over the past couple decades, hampered by high costs, low density, and lower endurance. But the number of proponents is growing.
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I'm not familiar with the technology but I thought the article was fairly in-depth and a good read.
It's a popular candidate for advanced foundry node memory embedded as a small part of an SoC or microcontroller, not standalone. Already too late to take away anything from 3D NAND or DRAM.
The density seems not a huge advance over SRAM, the article suggests double density. Well, if you use an optimized face-bonded SRAM chip like AMD's V-cache you almost double the density relative to the SRAM which is compiled to be compatible with a logic chip.
The other issue is speed. The signal from MRAM is weak so you need a good sense amp and time to integrate, which presumably translate to a bottleneck on access path per MB of storage. SRAM on a chip can provide tens of terabyte/sec throughput which is valuable for AI edge loads (not all the market, but almost all the new money looking for improved chips). Can MRAM come anywhere near that?
The density seems not a huge advance over SRAM, the article suggests double density. Well, if you use an optimized face-bonded SRAM chip like AMD's V-cache you almost double the density relative to the SRAM which is compiled to be compatible with a logic chip.
Yes, but you are still doubling your mm*2 of SRAM while doing that. You also need to hybrid bond the two dies which at least currently should be a yield hit, additionally the process does not seem to currently be running at a super high capacity (hopefully TSMC is working on expanding this alongside the rest of their advanced packaging expansion to make this cool tech more available). As you are no longer doing traditional packaging, packaging costs will increase potentially followed by thermals. The node you are stacking cache onto also needs to support TSVs, as well as said TSVs reducing area utilization of your base die.
Which isn’t to say I don’t think the technology has a place, because it seems the wind is blowing that way with the stagnation of SRAM scaling while logic keeps marching ahead. But it doesn’t seem like it will be the best choice for every application. Especially in this early stage while things aren’t mature yet.
Yep, advanced packaging is rapidly becoming a pain point. The problem is that the few pioneers like Sony imaging or AMD v-cache or YMTC Xtacking which prove it works, and works really well, open a flood of other companies that have similar needs but just were too small or too cautious to be pioneers. Now it is proven, they all want it, but capacity takes time to build.
If you don't really need SRAM performance and overall bandwidth that you can get from distributed embedded SRAM, then you have other choices. But, not if SRAM really is what you need.
It is mature enough. It just isn't cheap, and capacity is not available for all who want it.
Again, this is for where the foundry embeds some macro of NVM onto your SoC or microcontroller. They are really offering nothing (in terms of e-Flash) past 28nm node.
For standalone NOR (only NVM on chip), the market is very small, not much to say there. But in terms of increasing capacity upwards of Gb, it's going to run into 3D NAND eventually, especially as NAND has been touted as NOR replacement.
So for those of us designing ASICs with many cores on the edge with sane NRE budgets, can I assume that L1 cache uses SRAM, L2 will use a flavor of MRAM, and inductors must be avoided?
So for those of us designing ASICs with many cores on the edge with sane NRE budgets, can I assume that L1 cache uses SRAM, L2 will use a flavor of MRAM, and inductors must be avoided?
Foundries have mainly developed MRAM as a Flash macro replacement not SRAM replacement. The cell designs are quite different. Only Intel has come close with publishing a targeted last level cache application, obviously not in their chips (not yet at least).
Unfortunately, to access SSDs you need to do OS I/O operations, which are comparatively very slow and inefficient, even with the NVMe protocol, compared to memory accesses. The only currently-defined fix that comes to mind for individual SSDs would be RDMA support, which hasn't appeared due to cost and power challenges. NVMe over Fabrics supports RDMA, but for now this is only implemented by storage system servers, which only use RDMA in NVMe over Fabrics between the storage systems and the application servers, and even this use model for RDMA is not widely deployed. The storage industry also seems to be investing in the far slower NVMe over TCP protocol, because it's cheaper to implement in storage system servers and doesn't need RDMA-capable networking adapters.
semiengineering.com