The CFET (IBM's device) is very different from Huawei's "logic folding", even though, superficially, both involve some kind of stacking. From the design standpoint, the CFET is simply a rearrangement of P and N transistors within the standard cells: the two complementary transistors are just placed on top of one another, rather than side-by-side in the cell, as is currently done. Pin connectivity and intracell interconnects can also be a little more complicated with the CFET, but let's set that aside for now.
From the circuit design perspective (EDA), once a library of CFET standard cells is built, the rest of the design follows in the traditional way: all those cells are still located in the same 2D plane, so standard 2D design concepts can be used.
Logic folding, on the other hand, involves splitting chip designs or macro designs between two different planes of standard cells (actually coming from different wafers, in Huawei's case). For EDA tools, this is much more disruptive and difficult, and this could be Huawei's true breakthrough. Starting from the circuit schematics, the tool has to decide on which plane to place the circuit components, and utilize the two tiers so that both are efficiently packed with transistors.
In terms of process, CFET and Huawei's logic folding are also completely different: the core of the CFET process, as it is currently implemented by all chip makers, is in the front-end-of-line part of the flow (i.e. the part of the flow that deals with the transistor itself), and followed by interconnect patterning. The stacking is done by patterning both N and P transistors right after one another (or even at the same time, as in the case of the monolithic CFET). In Huawei's case, however, we start from two wafers with interconnected transistors, and bond them using bond pads located on the upper metal levels. The new process challenge involves hybrid wafer bonding at a relatively tight pitch (1.5um). Hybrid bonding is not trivial, but still orders of magnitude simpler than creating a manufacturable CFET process!
From the circuit design perspective (EDA), once a library of CFET standard cells is built, the rest of the design follows in the traditional way: all those cells are still located in the same 2D plane, so standard 2D design concepts can be used.
Logic folding, on the other hand, involves splitting chip designs or macro designs between two different planes of standard cells (actually coming from different wafers, in Huawei's case). For EDA tools, this is much more disruptive and difficult, and this could be Huawei's true breakthrough. Starting from the circuit schematics, the tool has to decide on which plane to place the circuit components, and utilize the two tiers so that both are efficiently packed with transistors.
In terms of process, CFET and Huawei's logic folding are also completely different: the core of the CFET process, as it is currently implemented by all chip makers, is in the front-end-of-line part of the flow (i.e. the part of the flow that deals with the transistor itself), and followed by interconnect patterning. The stacking is done by patterning both N and P transistors right after one another (or even at the same time, as in the case of the monolithic CFET). In Huawei's case, however, we start from two wafers with interconnected transistors, and bond them using bond pads located on the upper metal levels. The new process challenge involves hybrid wafer bonding at a relatively tight pitch (1.5um). Hybrid bonding is not trivial, but still orders of magnitude simpler than creating a manufacturable CFET process!
