You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!
A great article from Ian Cuttress -- partial take-aways to not spoil the full article:
- "When it comes to IBM, I firmly believe they’re in the camp of saying Moore’s Law is still alive."
- There are multiple types of CFET design in the literature, and specifically IBM has built a staggered sequential CFET design
- [Compared to IBM's 2nm - 40% SRAM scaling, 50% Logic scaling, more info in article]
- IBM is getting a High-NA machine..
The article also contrasts the major chip foundries approaches to future transistor types with what IBM is doing/planning, using plenty of charts and diagrams.
The really interesting bit is not just the PMOS/NMOS staggering but the fact that the NMOS and PMOS are on separately processed wafers which are cut on different crystal planes (<110> for PMOS, <001> for NMOS) to optimise the performance of each.
The key to all this is the new (proprietary?) "device-scale" wafer bonding process which IBM claim to have got working -- how this transfers to mass production remains to be seen, presumably any foundry which wanted to adopt the process will have to license this, and the differently-cut wafers, and the staggering.
All put together this offers some pretty compelling advantages, so it'll be interesting to see what the foundries (especially TSMC) do, adopt/license the IBM approach or try and come up with something of their own with similar advantages...
morethanmoore.substack.com
