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Monolithic three-dimensional integration of silicon transistors
Monolithic, three-dimensional (3D) integrated circuits promise advantages in packing density, energy consumption and interconnectivity bandwidth but require forming high-performance semiconductors and transistors on top tiers under the constraint of a limited thermal budget compatible with back-end-of-line integration.
Here we show that uniformly doped, ultrathin (≤10 nm) single-crystalline silicon nanomembranes can be vertically stacked using a roll-transfer-printing process that is scalable to wafer-scale and tolerant to substrate topology and surface roughness, enabling multi-tiers of complementary junctionless transistors to be sequentially fabricated on the same starting substrate under a processing temperature ≤400 °C.
These devices achieve performance approaching that of front-end-of-line silicon metal–oxide–semiconductor field-effect transistors with current density above 650 µA µm−1 and sub-10-nm inter-tier registration for high-density vertical integration.
We vertically constructed logic gates, including inverters, NAND, NOR gates and static random-access memory cells, based on up to three-tier integration at transistor-level granularity.
Uniformly doped, ultrathin single-crystalline silicon nanomembranes can be vertically stacked at low temperature using a roll-transfer-printing process that is scalable to wafer scale and tolerant to substrate topology and surface roughness for constructing high-performance monolithic...
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