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Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/threads/ment-wins-injunction-against-snps-for-emulation-patent-6-240-376.5705/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021770
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

MENT wins injunction against SNPS for emulation patent 6,240,376

Daniel Payne

Daniel Payne

Moderator
Emulation is a brisk growing segment for EDA companies like Mentor Graphics, Synopsys and Cadence. Mentor and Synopsys have been in litigation about emulators and today an Oregon Federal District Court gave an injunction ruling favorable to Mentor, stopping Synopsys from emulators covered by U.S. Patent No. 6,240,376.

Full Press Release Here

If Synopsys really did release a new version of software for the ZeBu emulator that doesn't violate this patent, then this may be pointless. As both companies draw out this legal process the lawyers are getting richer. Who knows if Mentor will ever collect the $36 million judgement from Synopsys.
 
From Synopsys:

Synopsys issued an announcement today stating that:
-- We will continue to sell, ship and support our ZeBu Server emulation systems worldwide;
-- We have released a new version of our ZeBu software that does not include the two features found to infringe.

Synopsys will immediately request a stay of certain aspects of the injunction and will appeal the injunction and the jury's infringement finding. Synopsys does not believe EVE, the original creator of ZeBu, infringed on U.S. Patent No. 6,240,376.

The text of today’s news release is inserted below for your reference, along with Synopsys’ announcement from October 10, 2014.

Synopsys Continues to Sell, Ship and Support ZeBu Emulation Systems Worldwide -- MOUNTAIN VIEW, Calif., March 12, 2015 /PRNewswire/ --
 
It's fascinating that Synopsys could simply make some code changes and now ZeBu doesn't infringe the patent. Here's the patent abstract:

Methods of instrumenting synthesizable source code to enable debugging support akin to high-level language programming environments for gate-level simulation are provided. One method of facilitating gate level simulation includes generating cross-reference instrumentation data including instrumentation logic indicative of an execution status of at least one synthesizable register transfer level (RTL) source code statement. A gate-level netlist is synthesized from the source code. Evaluation of the instrumentation logic during simulation of the gate-level netlist facilitates simulation by indicating the execution status of a corresponding source code statement. One method results in a modified gatelevel netlist to generate instrumentation signals corresponding to synthesizable statements within the source code. This may be accomplished by modifying the source code or by generating the modified gate-level netlist as if the source code was modified during synthesis. Alternatively, cross-reference instrumentation data including instrumentation logic can be generated without modifying the gate-level design. The instrumentation logic indicates the execution status of a corresponding cross-referenced synthesizable statement. An execution count of a cross-referenced synthesizable statement can be incremented when the corresponding instrumentation signals indicates the statement is active to determine source code coverage. Source code statements can be highlighted when active for visually tracing execution paths. For breakpoint simulation, a breakpoint can be set at a selected source code statement. The corresponding instrumentation logic from the cross-reference instrumentation data is implemented as a simulation breakpoint. The simulation is halted at a simulation cycle where the values of the instrumentation signals indicate that the source code statement is active.

Link to patent
 
Daniel Payne said:
It's fascinating that Synopsys could simply make some code changes and now ZeBu doesn't infringe the patent. Here's the patent abstract:

Methods of instrumenting synthesizable source code to enable debugging support akin to high-level language programming environments for gate-level simulation are provided. One method of facilitating gate level simulation includes generating cross-reference instrumentation data including instrumentation logic indicative of an execution status of at least one synthesizable register transfer level (RTL) source code statement. A gate-level netlist is synthesized from the source code. Evaluation of the instrumentation logic during simulation of the gate-level netlist facilitates simulation by indicating the execution status of a corresponding source code statement. One method results in a modified gatelevel netlist to generate instrumentation signals corresponding to synthesizable statements within the source code. This may be accomplished by modifying the source code or by generating the modified gate-level netlist as if the source code was modified during synthesis. Alternatively, cross-reference instrumentation data including instrumentation logic can be generated without modifying the gate-level design. The instrumentation logic indicates the execution status of a corresponding cross-referenced synthesizable statement. An execution count of a cross-referenced synthesizable statement can be incremented when the corresponding instrumentation signals indicates the statement is active to determine source code coverage. Source code statements can be highlighted when active for visually tracing execution paths. For breakpoint simulation, a breakpoint can be set at a selected source code statement. The corresponding instrumentation logic from the cross-reference instrumentation data is implemented as a simulation breakpoint. The simulation is halted at a simulation cycle where the values of the instrumentation signals indicate that the source code statement is active.

Link to patent
Click to expand...


To both Daniel, from the patent abstract, do you understand what's the patent really talking about? I read it several times and I can only see many common ideas and practices I learned from the computer science, nothing special.
 
Last edited:
hist78,
Unfortunately the engineers who write the original patent then hand it over to the legal department, which then re-writes the patent into an almost unrecognizable form, leaving most of us scratching our heads wondering what the original intentions were.

In general hardware designers code in RTL, then push a button to get this RTL code into a hardware emulator. Logic synthesis helps map the code into gates, and then while running the emulator you want to have breakpoints when certain logic events happen. Beyond that, the abstract makes little sense to me.
 
Daniel Payne said:
hist78,
Unfortunately the engineers who write the original patent then hand it over to the legal department, which then re-writes the patent into an almost unrecognizable form, leaving most of us scratching our heads wondering what the original intentions were.

In general hardware designers code in RTL, then push a button to get this RTL code into a hardware emulator. Logic synthesis helps map the code into gates, and then while running the emulator you want to have breakpoints when certain logic events happen. Beyond that, the abstract makes little sense to me.
Click to expand...

Remember the game where someone makes a statement, and you repeat the statement and add on the postfix..."in bed" ? It can get pretty funny. So can software patents!

The courts have been weighing in recently with the common-sense take that a software process is NOT patentable if all you did was take a manual procedure (e.g. algorithm)
and added on the postfix "with a computer".

See:
Software Patents Are Increasingly Coming Under Fire In Court | TechCrunch

This would separate out the hw from the sw in emulation patents...and of course totally change their value!

alan
 
Alan,

You have some experience with patents, both writing them and finding prior art to invalidate them. What is your take on this particular patent?
 
Ok, I looked at the patent for a few minutes...
It's about debugging support for simulations.

So, it's a software patent, about how to debug software simulations of hardware models.
There is no mention about prior art in the software debugging domain.
There are terms used, like "synthesizable", "gate level simulation"...but,without fully describing these terms and their context and limitations and physical presence, these descriptions are about "abstract models" executed on an "abstract computer"...hmmm...exactly what you'd do with pencil and paper..."abstractly"...

This is the problem with software patents. At best, they describe fixed recipes(algorithms) with an improvement...time, space, even machine dependent tricks(remember 64k memory limitations of processors)...the point is real improvements of specific measurable processes. At worst, they are very abstract, related more to abstract mathematical ideas and models. In between, where you mix the two, is where most software patents lie.

Any reasonable software engineer who works on some system for 3-6 months can generate a software patent, by just describing how they "coded" up the problem...why?...well, there are always many measurable algorithm, data structure, and execution methods that one uses to get to the end goal, and, all together, they are always "unique" and "innovative".

This patent probably made it though the gauntlet as it is well referenced by others, and references lots of others, so in the social media graph of patents, this one is "well connected", so therefore must be valid as it's friends are valid.

Finally, to you beginning question...how can you quickly release new software that doesn't invalidate this patent...well, this is where the "abstractness" helps! Just recode that piece using a different recipe...like replacing xanthan gum with agar agar in gluten free recipes! After all, it's software...and there are lots of ways to instrument your debugger!
 
hist78 said:
To both Daniel, from the patent abstract, do you understand what's the patent really talking about? I read it several times and I can only see many common ideas and practices I learned from the computer science, nothing special.
Click to expand...

Hi hist78,
My humble guess below:
There is a cross reference flag for both RTL description and gate level net list. bool X=0 as inactive, X=1 as active during emulation.
During debugging, for X=1, it is easy to modify active RTL to see how.
Since there could be billions of gate in SOC, this cross reference may needs special effort.
I think cross reference is not new. But the run time status for the cross reference application could be considered as innovation here.
 
Li,

When you talk about "X=0" do you mean X like an unknown state for a net, or are you talking about an arbitrary net named X? I just wanted to clarify my understanding.
 
The permanent injunction surprising quotes Intel as a Synopsys and Mentor customer, however this EDA customer is widely known for having a "no comment" approach to all vendors because they don't want to publicly endorse one vendor over another in order to drive down the price they pay to any vendor.
 
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