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A common way to define the size of a layout design is to give the number of nets.
How does compare to the number of interconnects?
For example, if we say that a layout includes 100K nets, what is the expected number of interconnects?
About the same order of magnitude or less?
What is your definition of interconnect ? Each net is one multi-point interconnect; e.g. for digital each net connects one output to one or more inputs.
I never counted them but each net will generate at least one resistor and one or more capacitances but on average I don't think it will be an order of magnitude. For capacitance it makes also big difference if you include coupling capacitances or just capacitances between signals and DC (rc or rcc extraction in Mentor Calibre parlor). For extraction with coupling included the resulting capacitance matrix will be highly sparse though.
The extracted # of R's and C's depends on the tool settings. At a minimum you would have one R and one C per net. For highly detailed layouts with adjacent interconnect, like an SRAM cell, then you want to extract Capacitors that are formed by adjacent interconnect segments, so the RC count for such a detailed extraction can be 10X the number of nets.
