Intel's Manufacturing Day Materials
- Thread starter Daniel Nenni
- Start date
Correct lefty, I truly believe that it was done on purpose (most likely was too good to show vs their 14++). Unfortunately I do not know what process is represented by the red triangles either. What I do know is that both 14LPP and 16FF+ are in the nmos graph, since they stated the cpps, respectively of 78 and 90nm. My educated guess is that they are 16FF+, since it would follow the same pattern of 14 and 14++ (the higher the cpp the better the xtor performance).
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There's a very interesting analysis of Intel's manufacturing claims at Semiaccurate: Is Intel's Hyperscaling really a change? - SemiAccurate
It's rather long winded, but the gist is
1) "hyper scaling" is not real. Intel altered the measurement of scaling of previous nodes to make the new nodes look like they are scaling more.
2) The charts showing reduced cost per transistor are misleading, because they assume perfect yields, but the yields are not perfect (especially for 10nm).
3) Mid node improvements (i.e. 14nm+ and 14nm++) is presented as a new development, but it isn't because they have being doing that all along, but just kept mum about it. (Haswell was really on a 22nm+ node, just that Intel kept that detail secret.)
It's rather long winded, but the gist is
1) "hyper scaling" is not real. Intel altered the measurement of scaling of previous nodes to make the new nodes look like they are scaling more.
2) The charts showing reduced cost per transistor are misleading, because they assume perfect yields, but the yields are not perfect (especially for 10nm).
3) Mid node improvements (i.e. 14nm+ and 14nm++) is presented as a new development, but it isn't because they have being doing that all along, but just kept mum about it. (Haswell was really on a 22nm+ node, just that Intel kept that detail secret.)
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S
Staf_Verhaegen
Guest
1) Blame the foundries with their marketing wars that removed any physical meaning from the nm in their node names. At least Intel is proposing something based not only on marketing power alone.
2) Give me any foundry that takes into account yield in their cost per transistor graphs.
3) This is valid remark, but at least they did not reduce the number in the node name...
I think the main problem in the end is that the trade-offs and decision to made in the nodes is so complicated that is can't be captured in a single node number/name anymore. But this naming still demanded by marketing...
I've been thinking about that slide showing transistor performance again. It is curious that Intel's 1st gen 14nm performs worse than the competitions 14/16nm, which are in reality a whole node behind Intel. If you compare the top boost clock of each generation of Intel's CPUs you see something quite interesting. Broadwell clocked very badly: the highest clocked SKU only reached 3.7 GHz (in fact slower than Haswell refresh). Then, when Skylake was released the clocks suddenly jumped to 4.2 GHz.
I would say that the first iteration of 14nm was a failure, insofar as that any new node should at least perform as well as the previous node. I think Intel quickly rolled out an improved version of 14nm for Skylake, but kept that detail secret. The chart shows Broadwell as the grey dots, Skylake is not shown, but it would fall in between Broadwell and Kaby Lake (14nm++).
I would say that the first iteration of 14nm was a failure, insofar as that any new node should at least perform as well as the previous node. I think Intel quickly rolled out an improved version of 14nm for Skylake, but kept that detail secret. The chart shows Broadwell as the grey dots, Skylake is not shown, but it would fall in between Broadwell and Kaby Lake (14nm++).
hist78
Well-known member
It doesn't make sense to me why Intel decided to abolish (or "retire" in Intel's words) this developer forum. I don't think that's a cost issue.
From Intel's news release:
I can't stop thinking this self-centered attitude Intel has displayed. It will lead Intel into trouble.
Another company recently got into big trouble because this kind of self-centered attitude is: United Airlines.
I'm okay with it. Originally it was a very technical conference but then the marketing people took over. I think they should also abolish manufacturing day. It really was ridiculous. They could have held it at the Intel HQ theater and saved thousands of dollars. They should also skip the high energy dance music, especially when introducing Mark Bohr!
Does anyone have materials/recordings from September China manufacturing day?
I have just seen some news such as 3GHz Cortex A75 at Intel's 10nm (i wish to know TDP or is it was mobile or server grade core) or 10nm FPGA "Falcon mesa" with 112Gbps transceivers (will not it be dual PAM4 or they just achieved breakthrough? just wondering).
I have just seen some news such as 3GHz Cortex A75 at Intel's 10nm (i wish to know TDP or is it was mobile or server grade core) or 10nm FPGA "Falcon mesa" with 112Gbps transceivers (will not it be dual PAM4 or they just achieved breakthrough? just wondering).
Here is a link: Intel發布10nm反擊台積電和三星，不過疲態已顯-中國新聞網
They had the "10nm" benchmark:
MMP: Intel 36 nm, TSMC 42 nm, Samsung 48 nm
CGP: Intel 54 nm, TSMC 66 nm, Samsung 68 nm
FinP: Intel 34 nm, TSMC 36 nm, Samsung 42 nm
Density: Intel 100.8 MTr/mm2, TSMC 48.1 MTr/mm2, Samsung 51.6 MTr/mm2
(some other dimension parameter is provided in the photo, but I do not know its meaning yet, e.g., if it is cell height)
They had the "10nm" benchmark:
MMP: Intel 36 nm, TSMC 42 nm, Samsung 48 nm
CGP: Intel 54 nm, TSMC 66 nm, Samsung 68 nm
FinP: Intel 34 nm, TSMC 36 nm, Samsung 42 nm
Density: Intel 100.8 MTr/mm2, TSMC 48.1 MTr/mm2, Samsung 51.6 MTr/mm2
(some other dimension parameter is provided in the photo, but I do not know its meaning yet, e.g., if it is cell height)
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The track number is not specified, but I don't know how they arrived at TSMC's pitch numbers, haven't seen those until now. The "cell height" doesn't help resolve the confusion either.
Edit: Intel uses some formula, maybe they applied to the others:
Let’s Clear Up the Node Naming Mess | Intel Newsroom
0.6*(NAND2 Tr count/NAND2 cell area) + 0.4*(Scan Flip Flop Tr count/Scan Flip Flop cell area) = # Tr/mm2
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