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Intel's Manufacturing Day Materials

Daniel Nenni

Daniel Nenni

Admin
Staff member
Definitely worth a look. Scott Jones is at the conference and will blog about it shortly:

Intel has been leading the pursuit of Moore’s Law for its entire existence. We have continuously advanced silicon technology and moved the capabilities of the industry forward. Today, the unmatched scope and scale of our investments in R&D and manufacturing ensure Intel continues to maintain industry leadership and drive innovation to provide our customers and consumers with leading-edge products in high volume.

Intel manufacturing processes advance according to Moore’s Law, delivering ever more functionality and performance, improved energy efficiency and lower cost per transistor with each generation. By continually advancing silicon technology and moving the industry forward, we empower people to do more, to enhance their knowledge, to strengthen their connections, to build the future, and to create and live in a smart and connected world.

https://newsroom.intel.com/press-kits/leading-edge-intel-technology-manufacturing/
 
They use the word hyperscaling a lot but Intel really doesn't say what it is. 10 nm is quad patterned.
 
Obfuscation. Here's the thing, this was nothing more than a dog and pony show for people who do not know any better. Semiconductor professionals already know the difference between processes. Before committing to a new process we use the PDKs to properly evaluate the differences. We do not use Power Point slides or clever charts.

Intel is an IDM not a foundry. Companies all over the world, including Apple, have evaluated Intel's PDKs at 22nm and 14nm and have rejected them. Why do you think 10nm will be any different?

Intel's 14nm FPGAs are supposed to be out now. Where is the reverse engineering report comparing Intel/Altera and Xilinx? Wouldn't that be the best way to compare Intel 14nm and TSMC 16nm? Better than Power Point obfuscation certainly.

Intel wants the industry to adopt a new formula for process naming? How about we use the one from an independent source (ASML):http://tinyurl.com/htr...

You must also include time which we did. Scott Jones, the author of this article, attended the event and will have much more to say on SemiWiki in the coming days, absolutely.

D.A.N.
 
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Their slides still don't recognise the existence of the competitions 7nm.
It looks like Intel's 2017 10nm launch will be before the yields are ready, purely as a PR exercise. It's interesting that the slides show 14nm reached high volume production in 2015, not 2014
Edit: I took the liberty of correcting Intel's slide ;):

View attachment 19478
 
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lefty said:
It's interesting that the slides show 14nm reached high volume production in 2015, not 2014
Click to expand...

Indeed.... I broke the 14nm yield problem story back in 2013:

Intel 14nm Delayed?
by Daniel Nenni
Published on 07-31-2013 08:45 PM
One of the more interesting pieces of information I overheard at SEMICON West earlier this month was that Intel 14nm was delayed. This rumor came from the semiconductor equipment manufacturers and they would know. What I was told is that the Intel 14nm process has not left the OR development facility to be replicated in the OR and AZ fabs….

No Mention of 14nm at the 2013 Intel Developer Forum?
by Daniel Nenni
Published on 08-19-2013 03:00 PM

Intel Really is Delaying 14nm Move-in. 450mm is Slipping Too. EUV, who knows?
by Paul McLellan
Published on 08-24-2013 01:23 PM

Intel Comes Clean on 14nm Yield!
by Daniel Nenni
Published on 12-04-2013 06:00 AM

Intel 14nm Delayed Again?
by Daniel Nenni
Published on 02-12-2014 07:00 AM

Intel 14nm Delayed Yet Again?
by Daniel Nenni
Published on 7-10-2014 10:00am
 
GF Response to the Intel 22FFL announcement sent to press/analysts:

Please see below for a comment from Globalfoundries in response to recent competitor announcements. Feel free to use this quote in any stories you may be writing, and let me know if you have further questions. We will also be sharing more details on our company blog in the near future.

“We are pleased to see competitors following our lead with the introduction of low-power 22nm processes. Almost two years ago, we launched our 22FDX FD-SOI technology for wireless, battery-powered intelligent systems,” said Alain Mutricy, SVP, Product Management Group at GF. “We chose FD-SOI over bulk planar or FinFET because it provides the best combination of performance, power and area for these applications. Our process is fully qualified for production and we are seeing strong customer demand, with more than 50 active engagements in high-growth areas such as mobile, IoT, and automotive.”
 
Daniel
There seems to have been no yield information given out by Intel for their 10nm process. Not even SRAM yield. The rumours of serious yield problems look to be quite true. Whats worse is Intel's first gen 10nm process is only slightly better than 14nm+ for transistor performance and inferior than 14nm++ . In fact even 10nm+ will not be better than 14nm++ and it will take 10nm++ sometime in late 2019 to provide better transistor performance. (slide 29 of the below pdf)

https://newsroom.intel.com/newsroom.../2017/03/Kaizad-Mistry-2017-Manufacturing.pdf

That bodes very badly for Intel's high performance desktop CPUs which are now easily able to hit 5 Ghz on Kabylake which is built on 14nm+. Coffeelake built on 14nm++ should do even better. We are unlikely to see such a high clocking CPU from Intel 10nm until late 2019 or early 2020. The reality is Intel will not have 10nm in 2017 even for PR bragging rights. We will see this confirmed by H2 2017. Intel has already confirmed the actual 10nm product volume ramp will be in H1 2018. I think we could see TSMC 7nm ramp serious volume in Q1 2018 for next year iPad first and then in Q2 2018 for iPhone. TSMC has confirmed 40nm minimum metal pitch at 7nm compared to Intel's 36nm minimum metal pitch for their process. The problem with Intel has always been their products do not showcase the so called superior transistor density. Atom failed miserably to leverage the so called superior Intel process to beat ARM chips on performance, power and size. With Zen we are seeing AMD compete pretty well on power consumption with a significantly inferior 14LPP process.
 
Indeed... what gets left out of these sort of investor focused presentations is often more telling than what gets put in. Having a manufacturing day that leaves out any discussion of yield implies that it's not a good story. If it was, they'd want to talk about it.

I do think they will release some kind of 10nm product for PR purposes, just like they just released an Xpoint product that appears to be only for PR purposes.
 
Daniel Nenni said:
Did you guys notice this slide? Are they saying that 14++ is faster than 10nm?
Click to expand...
It seems that way, although the chart shows 14nm+ being released in summer 2015 and 14nm++ released in spring 2016. That did not happen. Kaby lake was released in October 2016.
 
So, it looks like Scott's earlier sources on Intel's MMP being 40nm due to allegedly opting out of SAQP were wrong. Having a 36nm MMP combined w/ 5T cells instead of 6T cells for TSMC will ensure Intel's 10nm superiority over TSMC's 7nm. Intel will have that density crown for a while yet - unless GF/Samsung really hit it out of the park on their 7nm.
 
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TeemuSoilamo said:
So, it looks like Scott's earlier sources on Intel's MMP being 40nm due to allegedly opting out of SAQP were wrong. Having a 36nm MMP combined w/ 5T cells instead of 6T cells for TSMC will ensure Intel's 10nm superiority over TSMC's 7nm. Intel will have that density crown for a while yet - unless GF/Samsung really hit it out of the park on their 7nm.
Click to expand...
Except that Intel's 10nm is not 5 track, it's 7.5 track.
 
TeemuSoilamo said:
Does that mean they were using 11 track cells @ 14nm?

Can we deduce who is denser considering the dummy gate reduction?
Click to expand...
Nope. they are using 7.5 track at 14nm as well.
If you look at Kaizad Mistry's slides there is a bar chart in there that shows the density gains given by COAG and single DG. Those gains are about equal to the gains of using 6 track instead of 7.5.
 
lefty said:
Nope. they are using 7.5 track at 14nm as well.
If you look at Kaizad Mistry's slides there is a bar chart in there that shows the density gains given by COAG and single DG. Those gains are about equal to the gains of using 6 track instead of 7.5.
Click to expand...
I see. So, that would leave Intel with a slight edge over TSMC with the 36nm MMP. Of course, there may be additional factors that make a pure apples to apples comparison impossible.
 
What i like most is this slide https://3s81si1s5ygj3mzby34dq6qf-wp...el-moores-logic-transistor-density-metric.jpg and consequent comparison with competition https://3s81si1s5ygj3mzby34dq6qf-wp...es-logic-transistor-density-metric-others.jpg .

Intel promised here, that they will deliver stunning 100 MTr/mm2. Which is i must say, amazing. Even more amazing is, that others will deliver "just" 50 MTr/mm2 (which is i guess accurate number).

But lets look at other numbers they showed here. If we start from 45nm, they showed 3,3 MTr/mm2, which is i guess kind of accurate with delivered 3,08 Mtr. But if we look at the rest...

I made average of all Intels processors i know across nodes shown in slide, and here is the table:

[table] style="width: 411px"
|-
| style="height: 20px; width: 64px" | node
| style="width: 84px" | Intel slide
| style="width: 115px" | Intel delivered
| style="width: 149px" | Intel blend of reality
|-
| style="height: 20px" | 45
| 3,3
| 3,081652655
| 1,070853977
|-
| style="height: 20px" | 32
| 7,5
| 5,250487906
| 1,428438677
|-
| style="height: 20px" | 22
| 15,3
| 7,795977663
| 1,962550518
|-
| style="height: 20px" | 14
| 37,5
| 14,80648342
| 2,532674298
|-
| style="height: 20px" | 10
| 100,8
| ??
| ??
|-
[/table]
 
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Bohr himself made the point that "simply taking the total transistor count of a chip and dividing by its area is not meaningful because of the large number of design decisions that can affect it", i.e., cache sizes and performance targets that can cause great variations.

Yet, there is a clear trend here which is interesting. Hard to buy it being the result of merely different "design decisions", for sure.
 
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