Intel shares jump despite massive loss as chipmaker touts ‘solid progress’ cutting costs

[Xebec]

Here is the transcript:

Pat Gelsinger:

"we want to be a western Foundry at scale. And we think that's, that's Important, you know, for the Western world for the industry for Intel and that's the path that we've laid out."

Thanks --

I don't think he's wrong in what he says, the "Western World" isn't manufacturing as much as they used to, and that has a lot of long term implications. The USA got away from building nuclear power plants for so long that we're running out of experts to help design, build, and maintain them (effectively knowledge lost). Similar issues with NASA and Space, etc..

(Unfortunately we're also in an era where the US and world is trending away from free trade..)

Do you still think he was intending to disparage TSMC?

 

[Fred Chen]

It looks like the Intel 7 related charges are because there isn't enough reuse for Intel 4/3 and Intel 20A/18A. IIRC, TSMC shoots for at least 90% reuse.

 

[MKWVentures]

It looks like the Intel 7 related charges are because there isn't enough reuse for Intel 4/3 and Intel 20A/18A. IIRC, TSMC shoots for at least 90% reuse.

Funny. Pat changed depreciation from 5 years (was 4 before that) to 8 years because he said the useful life changed. This added BILLIONS to Intel earnings over the past 3 years

Now they said they are doing a one time write down as the useful life wasn't long. very convenient to give up all those earnings in a one time kitchen sink quarter. Should we start tracking book value trends?

Looks like none of the headcount reduction was in the Accounting/Finance area

 

[delong.height]

Yahoo Finance has an interview with Intel CEO Pat Gelsinger right after the earnings call. Unfortunately, Pat once again lost control of his mouth by first praising TSMC as an awesome partner and then immediately stating that TSMC is not a "Western world" foundry, while Intel is and wants to be a big one.

What exactly is the "Western world" that Pat Gelsinger is talking about? Does he mean that unless a company is owned and operated by people from a country established by the white European settlers, it can't be treated equally or trusted confidently?

If "Western world" means countries aligned with democratic political and free-market economic systems, then South Korea, Japan, and Taiwan (Republic of China) have been part of this "Western world" for a long time. Does Pat Gelsinger know that?

I don’t think Pat is a racist, but he really needs to watch his mouth as the CEO of Intel.

https://finance.yahoo.com/news/intel-ceo-calls-tsmc-an-awesome-company-says-the-company-is-still-waiting-for-chips-act-money-001504215.html?fr=sycsrp_catchall

Does the R&D for leading edge semiconductor manufacturing got done here? Noe it's done in Taiwan, and being outsourced to USA. TSMC does have foundry in western world but it's primarily for rebalancing geographic manufacturing capacity for ultra wealth company.

And no South Korea, Japan, and Taiwan have never been part of this western world. Militarily yes, culture-wise, NO.

 

[nghanayem]

It looks like the Intel 7 related charges are because there isn't enough reuse for Intel 4/3 and Intel 20A/18A. IIRC,

Intel did literally say that. Even just logically this should be obvious. Good example is M0 patterning. On Intel 7 that is 40nm (if memory serves) and done with spacer based pitch division. Okay sounds doable with dry DUV (160nm core feature) and with way more etch, dep, polish, and metrology tools to form the same feature. Intel talked about 18A using direct print EUV for fine pitch metal layers at SPIE. There is simply no way to carry over all of that extra dry DUV tools and extra supporting hardware. Also what tooling is "the best" is now different because what you are doing is different. That SAPQ process would presumably have to deal with much greater aspect ratios and very different hard masks and chemistries.

Another good public example is Co metal lines vs Cu metal lines with a Co liner. Intel 4 and GF 7LP papers have both shown that for metal lines that the hybrid approach offers superior performance AND acceptable EM lifetime. Even TSMC and Samsung were using this at their 16/14nm. But because Intel was on their island they did their process the Intel way on the Intel tooling rather than using what the industry conscience said was the most effective process/tooling combo. I have to imagine there are tons of other examples of different process segments where Intel in their isolation from the rest of the industry/vendors was doing something suboptimal from what others eventually figured out.

A final example is that 18A and beyond are GAA and BSPDN processes. Both introduce tons of brand new process modules and obsolete others. An example that immediately comes to mind is W fill of the RMG. I would assume CVD W is the most common way to fill it given you don't need to worry about shadowing, complex topologies, and that it is much faster than ALD. For GAA you have to fill W in places that can't be seen from above and I have to assume W fill would need to move to ALD W. I don't know enough about ALD to say for sure, but the complex 3D geometry might make it so PE ALD doesn't work and you need to do some low T thermal ALD to get inside all of those nooks and crannies.

TSMC shoots for at least 90% reuse.

Not really relevant since TSMC rarely converts fabs to newer process technologies. I also suspect that high tool reuse mostly occurs for sister nodes. ie 20nm/16FF, 10FF/N7, and N5/N3E. When you have to buy new equipment for your brand new fab anyways it makes no sense to use the old tooling unless it can do the job just as well for cheaper. Obviously in the world of memory or Intel's old pre foundry world, you want to maximize reuse. But TSMC'S business model doesn't heavily incentivise tool reuse outside of when process nodes don't have long decade plus volume tails.

Funny. Pat changed depreciation from 5 years (was 4 before that) to 8 years because he said the useful life changed. This added BILLIONS to Intel earnings over the past 3 years

Now they said they are doing a one time write down as the useful life wasn't long. very convenient to give up all those earnings in a one time kitchen sink quarter. Should we start tracking book value trends?

Looks like none of the headcount reduction was in the Accounting/Finance area

My understanding is that you can't change depreciation schedule mid life. Intel 7 would have been ramped up in the 2019-2021 timeframe (pre depreciation schedule change). If most of that equipment was on the 8 year timeline I suspect the write down number would have been a lot larger. As is, most intel 7 tooling should have been near the end of their depreciation lifetimes.

 

[KevinK]

Not really relevant since TSMC rarely converts fabs to newer process technologies. I also suspect that high tool reuse mostly occurs for sister nodes. ie 20nm/16FF, 10FF/N7, and N5/N3E.

That comment really nails it, and also points out that Intel hasn’t been able to prolong the lifetimes of the 7/4/3 fabs and tooling by offering foundry services for those nodes. That’s the magic of foundry economics - squeezing many profitable years out of fully depreciated fabs.

 

[MKWVentures]

My understanding is that you can't change depreciation schedule mid life. Intel 7 would have been ramped up in the 2019-2021 timeframe (pre depreciation schedule change). If most of that equipment was on the 8 year timeline I suspect the write down number would have been a lot larger. As is, most intel 7 tooling should have been near the end of their depreciation lifetimes.

you might be right on drepriciation. I would have to see the tool dep schedules to know ....

Didn't Pat Claim Intel 7 was one of the 5 nodes in 4 years he introduced? So it would have started have started after Pat arrived? or was it already delivered before he got there?

But Pat delivered 20A for sure...

 

[Daniel Nenni]

What about the Intel UMC collaboration to develop a 12 nm node? I would imagine the Intel 7 equipment could be used fort.

Is the Tower Semiconductor partnership dead? I thought they would do a UMC type of deal?

 

[Daniel Nenni]

Yahoo Finance has an interview with Intel CEO Pat Gelsinger right after the earnings call. Unfortunately, Pat once again lost control of his mouth by first praising TSMC as an awesome partner and then immediately stating that TSMC is not a "Western world" foundry, while Intel is and wants to be a big one.

What exactly is the "Western world" that Pat Gelsinger is talking about? Does he mean that unless a company is owned and operated by people from a country established by the white European settlers, it can't be treated equally or trusted confidently?

If "Western world" means countries aligned with democratic political and free-market economic systems, then South Korea, Japan, and Taiwan (Republic of China) have been part of this "Western world" for a long time. Does Pat Gelsinger know that?

I don’t think Pat is a racist, but he really needs to watch his mouth as the CEO of Intel.

https://finance.yahoo.com/news/intel-ceo-calls-tsmc-an-awesome-company-says-the-company-is-still-waiting-for-chips-act-money-001504215.html?fr=sycsrp_catchall

I'm guessing Western World includes Intel fabs in Israel and Ireland?

 

[MKWVentures]

Intel external foundry revenue, including all wafer sales, assembly packaging, and test was 67M in Q3.

Down 75% YoY.

 

[siliconbruh999]

Didn't they shelve the fab they were building in Israel ?

 

[Daniel Nenni]

Here is the transcript:
Pat Gelsinger:
"we want to be a western Foundry at scale. And we think that's, that's Important, you know, for the Western world for the industry for Intel and that's the path that we've laid out."

Is that how Intel will compete with TSMC? Excluding them because they are not Western world? Is that based on HQ location? Because TSMC has fabs in AZ, Japan, Taiwan, and will have fabs in Dresden and hopefully India. So TSMC is a world wide foundry and Intel is only Western world?

I really do not think this PR spin will work. Do you think this is something that was planned or did Pat jist riff this?

 

[Xebec]

you might be right on drepriciation. I would have to see the tool dep schedules to know ....

Didn't Pat Claim Intel 7 was one of the 5 nodes in 4 years he introduced? So it would have started have started after Pat arrived? or was it already delivered before he got there?

But Pat delivered 20A for sure...

A glass half full take -- Intel "10nm" was not clocking high (Icelake - 4.1-4.2 GHz) when Pat took over. They did get Tigerlake to about 5.0 GHz on the final 10nm node, but Intel 7 improved both absolute performance and perf/watt substantially (10-15% perf/watt vs Tigerlake's node). Given how modern node improvements are these days, this seems like a reasonable flag to plant.

I don't think Pat really did much to help this, if anything (i.e. already deep in the works) - but I haven't heard this forum seriously complain about Intel 7 being called a "7nm class node".

Regardless, if Intel 18A gets to high volume by the end of next year, that's a hugely improved position with respect to leading edge node capability vs. 2020.

 

[Xebec]

I feel like the oddball here - I heard "Western" as in western manufacturing.. not western world. It's OK if I'm the oddball..

Why not quote all the positive things Pat said about TSMC to give the full context?

 

[Fred Chen]

TSMC rarely converts fabs to newer process technologies. I also suspect that high tool reuse mostly occurs for sister nodes. ie 20nm/16FF, 10FF/N7, and N5/N3E. When you have to buy new equipment for your brand new fab anyways it makes no sense to use the old tooling unless it can do the job just as well for cheaper. Obviously in the world of memory or Intel's old pre foundry world, you want to maximize reuse. But TSMC'S business model doesn't heavily incentivise tool reuse outside of when process nodes don't have long decade plus volume tails.

At the same time, we haven't heard of a similar charge for TSMC's N7 when they went to N5. But we did hear of "margin dilution" when going to a new node. 90% node-to-node reuse is something to shoot for, but of course won't be possible with a fresh fab for a new node. Maybe the key difference here is N7 equipment will continue to be used, as opposed to Intel 7 seeming sunset.

18A and beyond are GAA and BSPDN processes. Both introduce tons of brand new process modules and obsolete others.

So this would be another financial burden coming up shortly, right? But it would be across the board for all players.

 

[blueone]

Is that how Intel will compete with TSMC? Excluding them because they are not Western world? Is that based on HQ location? Because TSMC has fabs in AZ, Japan, Taiwan, and will have fabs in Dresden and hopefully India. So TSMC is a world wide foundry and Intel is only Western world?

I really do not think this PR spin will work. Do you think this is something that was planned or did Pat jist riff this?

Whenever PG makes one of his oddball comments, I often wonder how high the cringe-factor gets on the Intel BoD. I bet he's setting new records lately.

 

[Fred Chen]

Good example is M0 patterning. On Intel 7 that is 40nm if memory serves with spacer based pitch division. Okay sounds doable with dry DUV (160nm core feature) and with way more etch, dep, polish, and metrology tools to form the same feature. Intel talked about 18A using direct print EUV for fine pitch metal layers at SPIE. There is simply no way to carry over all of that extra dry DUV tools and extra supporting hardware. Also what is good is now different. That SAPQ process would presumably have to deal with much greater aspect ratios and very different hard masks and chemistries.

The M0 and M1 of Intel 7 are a good example of processes which are essentially dropped.

They went from pure Co to Cu/Co, and the M0 and M1 pitches trended oppositely, M1 going back to almost the same as 14nm. Obviously, Intel 3 reused Intel 4 in this part.

 

[nghanayem]

Is the Tower Semiconductor partnership dead? I thought they would do a UMC type of deal?

That wasn't a co-development situation like with UMC. That was just running as a second source capacity upside for Tower 65nm. Also, that was in Fab 11/11X in NM which never ran an intel logic technology past 32nm. Funnily enough, they even have it on their website as if it is their fab, which made me chuckle a little bit when I first saw it.

Didn't they shelve the fab they were building in Israel ?

The rumor was that they would finish F38 in IS, but 48 would get the shell closed up and then be left empty until they decided which process they wanted to run there. But there has still been no official word on that. If it was true you would think they would have specifically mentioned it when they announced the various capacity deferments they were making in Malaysia for 3D package test, Germany fabs, and Poland 2D assembly test?

At the same time, we haven't heard of a similar charge for TSMC's N7 when they went to N5. But we did hear of "margin dilution" when going to a new node. 90% node-to-node reuse is something to shoot for, but of course won't be possible with a fresh fab for a new node.

Yeah, there is no reason to worry about that because N7 is still trucking along. N5 only ever ran in F18 (which was a brand-new site that was gradually built out to the full 6 phases exclusively for N5/N3 production). Granted, their N7 utilization this and last year was anemic, but that was unexpected and is very unusual. TSMC is normally very good at filling in customers as their leading edge design wins move onto bigger and better things by extending the capabilites and features (RF, MRAM, ReRAM, HV, LV, LL, TSV, CIS, etc.). Intel 7 would have always been sunset at some point on account of it not being a foundry technology and intel the IDM not having an indefinite usecase for any 7"nm" class node, but at least with chipsets/PCDs it would have been able to last longer and had a larger volume production tail.

Maybe the key difference here is N7 equipment will continue to be used, as opposed to Intel 7 seeming sunset.

Considering TSMC still runs and makes record revenues from ancient late 90s and 2000s process technologies, I would not be shocked in the slightest if N7 is still trucking along 20 years from now.

So this would be another financial burden coming up shortly, right? But it would be across the board for all players.

Not really? Intel had to build brand new EUV compatible fabs anyway (As D1X mods 1-3 and F42 were the only fabs intel had built post like 2006). Said new fabs would have always needed new equipment to fill them even if they were going to be running intel 14nm. So their capex plans would have been built around F42-62 and D1 having minimal intel 7 tool reuse. Same with TSMC F20 is being built from scratch so tool reuse isn't a concern. Having to rip up the whole FEOL process and start from scratch for HNSs was also something that would have been well known to all of the big three. It happened with HKMG and finFET. There was no reason to expect that they wouldn't be huge process flow changes for GAA especially given how the "all around part" impacts how you make not just the gate or the channel (HKMG and finFET respectively). But everything up until the contacts segment.

 

[tedc]

My understanding is that you can't change depreciation schedule mid life. Intel 7 would have been ramped up in the 2019-2021 timeframe (pre depreciation schedule change). If most of that equipment was on the 8 year timeline I suspect the write down number would have been a lot larger. As is, most intel 7 tooling should have been near the end of their depreciation lifetimes.

Exactly. It seems like forever ago, but Intel only announced the depreciation change in January 2023.

Is this the just the tip of the iceberg on schedule change impacts? If 18A is the first true foundry node, I have trouble seeing how 4/3/20 are still around after 8 years.

 

[kevin01]

Exactly. It seems like forever ago, but Intel only announced the depreciation change in January 2023.

Is this the just the tip of the iceberg on schedule change impacts? If 18A is the first true foundry node, I have trouble seeing how 4/3/20 are still around after 8 years.

Intel 7 uses DUV, while 3 and 18A primarily use EUV. Furthermore, Intel 7 seems to be a quite expensive process, relative to what it delivers; Intel has publicly said so several times. It is reasonable for them to deprecate Intel 7 in an accelerated fashion.