Intel Foundry is way behind TSMC, but the goal is #2 by 2030

[siliconbruh999]

I not you did not contest my assertion that Gelsinger over-promised and under delivered. To my mind that is a fatal flaw in the CEO of a semiconductor Foundry. Your customers must know that you will deliver what you promise and deliver it on time. The execution on 5N4Y was 6-12 months late. It was an impressive feat to get back in the game after so many missteps, but it took longer that Intel promised.

The issue with 5N4Y or the fab strategy is they put their foot on too many places they should have sticked to US or one more country not put their hand everywhere

14A under Tan seems to be looking better in regards to schedule, so I give that point to Tan.

Yeah but credit for revitalizing foundry should go to Pat otherwise Tan wouldn't have anything worthwhile to sell

Intel's public statements have been that they are under capacity on Intel 10/7. For the record Intel began selling off 7nm tooling in Oct'24. That was under Gelsinger. From the linked article:
"However, $3.1bn of the charges, related mainly to a writedown of equipment that had been acquired to make chips on the Intel 7 manufacturing node, were taken against non-GAAP profits.
David Zinsner, chief financial officer, told the Financial Times.... A lot of it never got unpacked, it was sitting on the sidelines waiting to be used."

The underlying cost structure of 18A is better than Intel 3. The issue right now is a lack of demand (i.e. not enough volume to fill the fabs) and yields that are below target and are having a negative effect on profitability.

They don't have server product on 18A till end of year anyway 18A is client node at least for the year

Panther Lake was already on the drawing boards and was not affected by the decision to go with unified core in the future. Gelsinger also made the decision to eliminate hyperthreading, which customers reportedly want and that feature is being reintroduced. I have seen no indication that Tan intends to pursue the unified core initiative.

It's more likely made by the core team to save time considering Panther Cove is a big change they are adding few new ISA Extension like and bunch of stuff AMD meanwhile simply being a follower is reaping on fruits sown by Intel in software and ISA as for unified core it was replacement for Royal Cove under Swan which failed miserably to meet the targets there are rumor going on that it was a 10mm2+ core on N3/18A which is not good.

Introducing Intel® Advanced Performance Extensions (Intel® APX)

These extensions expand the x86 instruction set with access to registers and features that improve performance.

www.intel.com

Intel® Advanced Vector Extensions 10.2 (Intel® AVX10.2) Architecture Specification

This document describes the Intel® Advanced Vector Extensions 10.2 Instruction Set Architecture.

www.intel.com

 

[my_wing]

"The failure of Gelsinger's "build it and they will come" approach is just one example to prove this point."

That is what you said while my answer is that Tan opened admit that Intel have no capacity, the point is that Tan was part of the Intel Board, he directly reduced capacity based on incorrect assessment of the forecast, at the end Pat is right, even only Intel alone they under build Intel 3 and 18A, if they are not under build, they can have sell a lot more CPU no matter it is Xeon 6 or Xeon 7 (i.e. not needed to wait until Q2 2026)

"Nowhere in the article you posted do I see Tan saying he was wrong" - That is where in the article.
""In the short term, I'm disappointed that we are not able to fully meet the demand in our markets," Chief Executive Officer Lip-Bu Tan told analysts on ‌a conference call."
As mentioned, Tan was playing a leading role inside the broad decide that Intel 3 capacity should be X, I'm disappointed that "we" ... what is we , in other words we can be equal to me and my team as Tan was part of the "we" i.e. part of the broad.
Normally, if he have little or no influence towards the mentioned AI under capacity, a normal person under him will said something like this (the salary and job security is on the line)
"In the short term, due to decision of prior management, the current demand in our market can't be met"

5N4Y was 6-12 months late:
Just asked CC Wei, TSMC never delay, they just rename, in general 12 months late is kinda of within the range of acceptable. By the way, due to the fact that now i.e. for the next 6 months, 18A is compare aganist N3P, and it just show by the performance that 18A is in general better than TSMC N3P, so 5N4Y will be remember as a success under Pat.

"Intel's public statements have been that they are under capacity on Intel 10/7. ..."
No this is not the case the see article I referenced, Intel shortage is at AI data center chip, the current Intel AI and Data Center chip is Xeon 6 and it is based where Sierra Forest is Intel 3 and only the IO of Granite Rapids is Intel 7. Intel current under capacity is Intel 3, that is what Tan decision from the broad is stop. He admitted it "we" including himself.


" "However, $3.1bn of the charges, related mainly to a writedown of equipment that had been acquired to make chips on the Intel 7 manufacturing node, were taken against non-GAAP profits.
David Zinsner, chief financial officer, told the Financial Times.... A lot of it never got unpacked, it was sitting on the sidelines waiting to be used." "

Another Bill that Pat is not liable to be paid and you assume that Pat needed to paid, Intel 7 was the previous Intel 10+++, The earliest Intel document on that node dated back to 2015, and when Pat is the CEO 2021, why Pat needed to pay for this bill.

"The underlying cost structure of 18A is better than Intel 3. The issue right now is a lack of demand (i.e. not enough volume to fill the fabs) and yields that are below target and are having a negative effect on profitability"
How ? Source ? 18A cost structure is better than Intel 3 ? OIC, because TSMC just raise price 30% each node from N4 i.e. N4 > N3B ~N3E > N3P > N2 using compound interest 30% each node does go > price increase of 100% i.e. 1.3^3, yes then Intel 18A does have a better cost structure. Tan already said that due to AI 18A demand is higher than Intel 3 sorry your point make no sense, Clearwater Forest is tape out and according to current schedule i.e. Q2 2026, then 18A is already at Risk Production or HVM, as mentioned, all AI Data Center chip is book out i.e. Intel 18A capacity is fully book out. And "we" include Tan ban down what Pat is estimated, Tan need to responsible for this lost in revenue.

"Panther Lake was already on the drawing boards and was not affected by the decision to go with unified core in the future."
This just make you known by all logical reader understand that you are bias, Panther Lake is 18A, 18A is designed directly under Pat and its related product i.e. Panther Lake (new eCore updates), Panther Lake is the first processor that Pat is in charge, Lunar Lake, arrow lake is the last processor that Bob swarm is in charge, why, Bob push for TSMC Fab and Pat push for IFS, the same goes Lunar Lake, Arrow Lake is TSMC and Panther Lake is IFS.

You are also welcome to have your opinion, but your opinion needed to make sense.

 

[Artificer60]

"The failure of Gelsinger's "build it and they will come" approach is just one example to prove this point."

That is what you said while my answer is that Tan opened admit that Intel have no capacity, the point is that Tan was part of the Intel Board, he directly reduced capacity based on incorrect assessment of the forecast, at the end Pat is right, even only Intel alone they under build Intel 3 and 18A, if they are not under build, they can have sell a lot more CPU no matter it is Xeon 6 or Xeon 7 (i.e. not needed to wait until Q2 2026)

"Nowhere in the article you posted do I see Tan saying he was wrong" - That is where in the article.
""In the short term, I'm disappointed that we are not able to fully meet the demand in our markets," Chief Executive Officer Lip-Bu Tan told analysts on ‌a conference call."
As mentioned, Tan was playing a leading role inside the broad decide that Intel 3 capacity should be X, I'm disappointed that "we" ... what is we , in other words we can be equal to me and my team as Tan was part of the "we" i.e. part of the broad.
Normally, if he have little or no influence towards the mentioned AI under capacity, a normal person under him will said something like this (the salary and job security is on the line)
"In the short term, due to decision of prior management, the current demand in our market can't be met"

5N4Y was 6-12 months late:
Just asked CC Wei, TSMC never delay, they just rename, in general 12 months late is kinda of within the range of acceptable. By the way, due to the fact that now i.e. for the next 6 months, 18A is compare aganist N3P, and it just show by the performance that 18A is in general better than TSMC N3P, so 5N4Y will be remember as a success under Pat.

"Intel's public statements have been that they are under capacity on Intel 10/7. ..."
No this is not the case the see article I referenced, Intel shortage is at AI data center chip, the current Intel AI and Data Center chip is Xeon 6 and it is based where Sierra Forest is Intel 3 and only the IO of Granite Rapids is Intel 7. Intel current under capacity is Intel 3, that is what Tan decision from the broad is stop. He admitted it "we" including himself.


" "However, $3.1bn of the charges, related mainly to a writedown of equipment that had been acquired to make chips on the Intel 7 manufacturing node, were taken against non-GAAP profits.
David Zinsner, chief financial officer, told the Financial Times.... A lot of it never got unpacked, it was sitting on the sidelines waiting to be used." "

Another Bill that Pat is not liable to be paid and you assume that Pat needed to paid, Intel 7 was the previous Intel 10+++, The earliest Intel document on that node dated back to 2015, and when Pat is the CEO 2021, why Pat needed to pay for this bill.

"The underlying cost structure of 18A is better than Intel 3. The issue right now is a lack of demand (i.e. not enough volume to fill the fabs) and yields that are below target and are having a negative effect on profitability"
How ? Source ? 18A cost structure is better than Intel 3 ? OIC, because TSMC just raise price 30% each node from N4 i.e. N4 > N3B ~N3E > N3P > N2 using compound interest 30% each node does go > price increase of 100% i.e. 1.3^3, yes then Intel 18A does have a better cost structure. Tan already said that due to AI 18A demand is higher than Intel 3 sorry your point make no sense, Clearwater Forest is tape out and according to current schedule i.e. Q2 2026, then 18A is already at Risk Production or HVM, as mentioned, all AI Data Center chip is book out i.e. Intel 18A capacity is fully book out. And "we" include Tan ban down what Pat is estimated, Tan need to responsible for this lost in revenue.

"Panther Lake was already on the drawing boards and was not affected by the decision to go with unified core in the future."
This just make you known by all logical reader understand that you are bias, Panther Lake is 18A, 18A is designed directly under Pat and its related product i.e. Panther Lake (new eCore updates), Panther Lake is the first processor that Pat is in charge, Lunar Lake, arrow lake is the last processor that Bob swarm is in charge, why, Bob push for TSMC Fab and Pat push for IFS, the same goes Lunar Lake, Arrow Lake is TSMC and Panther Lake is IFS.

You are also welcome to have your opinion, but your opinion needed to make sense.

It is clear you and I will never agree on this point, though personal insults are not necessary. I'm not particularly interested in an argument for argument's sake.

I guess the old adage is true. A man convinced against his will is of the same opinion still.

 

[my_wing]

It is clear you and I will never agree on this point, though personal insults are not necessary. I'm not particularly interested in an argument for argument's sake.

I guess the old adage is true. A man convinced against his will is of the same opinion still.

I further point out as the article come in today:

Intel Nova Lake die sizes leak, signaling higher cost — smaller compute tile still demands higher price on TSMC N2

But that is with bLLC.

www.tomshardware.com

The point just clearly shows that 18A is fully book out, and if you want to argue with the Yield then go for it, because of trade secret, Intel will never disclose the true yield rate of 18A, but in order to feed the Laptop market where 75% plus and Panther Lake is so well received, the end Intel laptop market is going to take share back from Apple as well, this is how I see it. That is why some of the early comments is counting the EUV machine that Intel / TSMC / Samsung have, is to estimate the true yield, I agree with the calculation to certain extend, but just want to highlight that the EUV machine that Intel is using is some of the newest, the backlight i.e. directly impacted throughput is the strongest, the machine Intel has can be as much as 100% higher throughput then the initial design of what TSMC has, but of course it is already around 10 years, the lighting equipment having a much lower life span (I think I saw this from Gigaphoton / another EUV light source before ASML acquired Cymer), with an updated light source, the EUV throughput of these initial machine should have increased.

The article show how under capacity Intel 18A, please see the IanD part of this post, please check how different it is to design BSPD Vs FSPD, there is no option for the compute tile to be N2 class, how I see this is that news article is not that accurate, the things is very difficult to achieve.

Talk about hyperthreading:
There is only handful of people luck enough to be in the ASIC design team to verify, what Intel is say is that Cost Vs Benefit i.e. Die Space Vs Performance, hyperthreading works if all cores are full of task i.e. in benchmarking / HPC and the data set has very little to do with I/O, I think currently I/O is the bottleneck and it was since a long long time, there is a lot of trade off that we without the luck to be a Intel / AMD / Apple / ARM Designer can never simulate and tell you. This is a wait and observe types of question and I honestly can give an opinion.

Royal Core that referred to Jim Killer project
That project is killed, it was and still it is killed, I could be very bias in this one, as I am a supporter of VLIW and not a big fan of X86-64 or AMD64 nor RISC, I preferred to skip this one, but it is another misread about big.little vs royal core, as royal core is a concept, and the concept document is basically saying that within CPU core you have register / execute unit / FPU / SIMD / branch predict / scheduler .... and each have a specific pre-defined number, what if and what if we can dynamically shape these resource into Rentable units and dynamically allocate the die space. Okay, this is far to complex, and as I am the supporter of VLIW, in short I would love the world where these things is handle as much as possible by the compiler.