Intel Foundry is way behind TSMC, but the goal is #2 by 2030

[siliconbruh999]

Without High NA EUV
Without Dry Photoresist
Without Pattern Sharpening

Only rely on Double / Quad Patterning, we know the story of Intel 14nm++++++
Good luck, we saw that road and that don't seems to work (one is Intel 14nm / 10nm then is the N3B)

are the number of plus in 14nm correct? I thought there were only 5 plus

 

[IanD]

">20% density gain ... full-node scaling" = trigger warning for me

That's the reality nowadays -- basic pitches that set cell size (M0 and CPP) are almost identical for N3/N2/A16/A14, the gate density increases come mainly from other layout/library tweaks usually referred to as DTCO, with labels such as FlexFin and NanoFlex and NanoFlex Pro (and BSPD, and COAG, and SDB, and...) -- or other "special" design rules only allowed in very specific layout regions, like those TSMC introduced in N2 to lower access resistance and parasitic capacitance in "digital-only" areas. Plus the fact that nanosheet gives more drive current in a given area than finFET, so minimum size gates are faster and high drive gates are smaller.

In other words "full-node scaling" is largely a fiction nowadays, it doesn't really mean scaling any more at all -- it means the next node with a different set of design rules and new DTCO enhancements, as opposed to a "half-node" which means the same process tweaked to improve PPA slightly (e.g. 10%)... :-(