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Intel CEO embraces its 18A node for external customers as 18A-P gets 'inbound interest' — company cites increasing yields

Fred Chen

Moderator
By Anton Shilov published March 5, 2026
But Intel is not out of the woods with its 18A node.

When Lip-Bu Tan came to Intel last year, he considered stopping the promotion of the company's 18A (1.8nm-class) fabrication technology among potential external customers and making it yet another internal-only node, as he did not believe the manufacturing process made a lot of sense for external clients. Less than a year later, he seems to have changed his mind about the prospects of the fabrication process to a large degree because some external customers expressed interest in 18A-P, a performance-enhanced version of 18A. Yet, Intel admits that 18A continues to suffer from process variability.

"While Lip-Bu was, I think, thinking that we probably should focus on 14A as a foundry node and make 18A really just an internal node, now that we have seen some real progress there, I think he is now starting to recognize that this is actually a good node to offer to external customers as well," said David Zinsner, chief financial officer of Intel, Morgan Stanley Technology, Media & Telecom Conference 2026. "We have been getting some kind of inbound interest in 18A-P as a foundry node. So, I think that is pretty positive."

When Lip-Bu Tan joined Intel in early 2025, both the functional and parametric yields of chips made using 18A were low and unpredictable. As a result, Tan reportedly considered shifting the company's foundry efforts to 14A (1.4nm-class) instead in a bid to focus on large clients who make strategic decisions about production nodes many years in advance and had opted to not use 18A at the time.

Intel made some progress on 18A yields in late 2025, in time to start low-volume production of the company's Core Ultra 300-series 'Panther Lake' CPU tiles at a development facility in Oregon while beginning to ramp high-volume manufacturing at its Fab 32 in Arizona. Intel admitted that 18A yields were only set to reach industry standard levels in 2027, but insisted that it was on the right trajectory. While it may indeed be on the right trajectory, Intel still suffers from process variability (though again, we do not know whether Intel means functional or parametric yields, though the latter is more likely), which is typical for early stages of HVM ramp.

"There is a lot of volatility, […] some wafers are yielding a lot less and some are yielding a lot more," Zinsner said. "[Tan] is actually focused a lot on trying to minimize the volatility wafer to wafer, and we have made good improvement there. […] I think we would expect a pretty steady yield progression as we go through this year, probably a bit ahead of schedule."

If wafer-to-wafer parametric variation is high but improving, this is not something unusual, especially keeping in mind that Intel's 18A introduces gate-all-around RibbonFET transistors and backside power delivery, two previously unknown technologies. However, depending on how significant process variability is, parametric yield volatility creates capacity unpredictability, which makes supply planning hard. As a result, it is not surprising that Intel's CEO thought about ceasing the promotion of 18A as a foundry node, as the company did not have visibility on when it could offer it to external customers without creating supply constraints for itself.

Based on the recent rumors, a number of big fabless chip designers have evaluated Intel's 18A and 18A-P process technologies, though none have made any publicly-announced commitments to use the node. Nevertheless, it is possible that at least some of America's chip developers may outsource production of some of their non-core products to Intel in the coming years to increase production of their silicon in the U.S. to reduce their geopolitical risks associated with Taiwan and potential tariffs on chips made outside of America.


 
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Fred, how do you know 18A yield variation is due to EUV, vs. other node innovations such as the nanoribbons and powervia??
The large swings of yield can come from the intrinsic variation of stochastic defect density, but other systematic factors related to process control can also be contributing, perhaps comparably.
 
The large swings of yield can come from the intrinsic variation of stochastic defect density, but other systematic factors related to process control can also be contributing, perhaps comparably.
18A minimum pitch is 36nm, a relatively "easy" pitch for EUV, and which the industry already also has experience with. So I don't see how EUV stochastic effects would have a significant effect on yield in this case.
 
18A minimum pitch is 36nm, a relatively "easy" pitch for EUV, and which the industry already also has experience with. So I don't see how EUV stochastic effects would have a significant effect on yield in this case.
36 nm pitch has significant stochastic defectivity, which has been reported by Samsung and others (first by IMEC).

Samsung also confirmed the issue here as well: https://www.spiedigitallibrary.org/...ure-model-for-random/10.1117/12.3050663.short.

Also disclosed by Siemens EDA here: https://www.spiedigitallibrary.org/...UVL-stochastic-aware/10.1117/12.3010912.short.
 
36 nm pitch has significant stochastic defectivity, which has been reported by Samsung and others (first by IMEC).

Samsung also confirmed the issue here as well: https://www.spiedigitallibrary.org/...ure-model-for-random/10.1117/12.3050663.short.

Also disclosed by Siemens EDA here: https://www.spiedigitallibrary.org/...UVL-stochastic-aware/10.1117/12.3010912.short.
Feel like Intel people dont know the fundamentals well enough and yet try to resolve something impossible?
 
Intel's process variability is at least partially a result of their historical needs. As a CPU manufacturer they have always been able to bin their products. Runs a bit slow, drop it into a lower performance bin. Runs faster, bin it as a high performance SKU. So the fact that they can bin their product and still sell it means that they do not have as pressing a need to nail down the variability as manufacturers developing other products do. As a result the financial math made variability reduction a lower priority. Combine this with the relatively short life span of their products and it becomes apparent why they are struggling with variability now. Reducing variability was always desirable, but was further down the priority list than some other items.

As Intel moves into trying to land customers that don't have the tolerance for variability this is now becoming an area of focus. Intel has a track record of solving difficult process problems so I'm sure they will get this figured out, but up until now it has been less of a priority for them.
 
36 nm pitch has significant stochastic defectivity, which has been reported by Samsung and others (first by IMEC).

Samsung also confirmed the issue here as well: https://www.spiedigitallibrary.org/...ure-model-for-random/10.1117/12.3050663.short.

Also disclosed by Siemens EDA here: https://www.spiedigitallibrary.org/...UVL-stochastic-aware/10.1117/12.3010912.short.
The Apple Neo macbook just show that TSMC do also experience Yield issues in TSMC. As this can meant that there is so many unusable iPhone chip with 1 GPU less laid around.

The educated guess is that TSMC N3E D0 is around 0.2 - 0.3, which is not what TSMC usually promote at D0 < 0.1 for HVM.
 
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