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Then do we have front pads(which is connected to DRAM and platform) and back pads(power and ground) now? AFAIK Intel 3nm PowerVia test chip (E-core chip) didn't look like that.
No, the normal I/O pads are on the backside along the the power rails and PWR/GND pads -- also anything else that needs thick low-resistance metal e.g. inductors and transmission lines in high-speed SERDES.