? How Many Patents are about Costs?

[Arthur Hanson]

Once an advanced patents are about lowering costs of existing nodes, rather than advancing them? How fast does the costs of advanced nodes go down and what companies have mastered it? Also, how many patents cover the average leading edge nodes? Additional comments on this would also be appreciated.

 

[nghanayem]

Once an advanced patents are about lowering costs of existing nodes, rather than advancing them?

Could you rephrase this? Are you asking do semi firms make patents about lowering wafer cost? Also advancing nodes is equivalent to reducing the costs of new nodes. Obviously wafer costs go up (it always has and always will), but cost per transistor falls.

How fast does the costs of advanced nodes go down and what companies have mastered it?

Given the heavy fixed costs of running a fab the biggest thing that reduces wafer cost is when the tools have deprecated. Besides that process recipes can be tuned to reduce chems costs or improve yield, finding ways to make tool maintenance a bit cheaper, extending the life between tool maintenances, optical shrinks can help as they improve density without substantially changing wafer costs, as well as cost optimized versions of nodes (think N4, N6, 14LPC, 22GP, and intel 16).

 

[Arthur Hanson]

Could you rephrase this? Are you asking do semi firms make patents about lowering wafer cost? Also advancing nodes is equivalent to reducing the costs of new nodes. Obviously wafer costs go up (it always has and always will), but cost per transistor falls.


Given the heavy fixed costs of running a fab the biggest thing that reduces wafer cost is when the tools have deprecated. Besides that process recipes can be tuned to reduce chems costs or improve yield, finding ways to make tool maintenance a bit cheaper, extending the life between tool maintenances, optical shrinks can help as they improve density without substantially changing wafer costs, as well as cost optimized versions of nodes (think N4, N6, 14LPC, 22GP, and intel 16).

Is it possible to change a design or a tool or are these fixed and not able to be changed or modified, or the expense to great? Can part of the process be changed after initial production or is the entire process fixed.

 

[nghanayem]

Changes can be made and new tools can be inserted, but there are caveats here. N7+ is a good example here where EUV got inserted at multiple layers. This insertion forced new design rules/retape out, and added a bunch of upfront cost to add EUV tools to N7 fabs. Another example would be Samsung 4LPE changing how the contacts are formed from previous 7LPP family nodes. The new contact scheme also required either new or upgraded tools. Smaller continuous improvements to variability/DD/performance can also be made to current nodes without any change to tools or the masksets (see Samsung and Qualcomm's recent IEDM paper on the improvements made to 5LPE/4LPX as an excellent example of this).