Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/threads/exclusive-asml-unveils-euv-light-source-advance-that-could-yield-50-more-chips-by-2030.24600/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2030970
            [XFI] => 1060170
        )

    [wordpress] => /var/www/html
)

Exclusive-ASML unveils EUV light source advance that could yield 50% more chips by 2030

Daniel Nenni

Admin
Staff member
e4fbf22a754c7a5c37f083efaaf519c7

ASML reports Q4 earnings, in Veldhoven · Reuters

SAN DIEGO, California, Feb 23 (Reuters) - Researchers at ASML Holding say they have found a way to boost the power of the light source in a key chip making machine to turn out up to 50% more chips by decade's end, to help retain the Dutch company's ‌edge over emerging U.S. and Chinese rivals.

ASML is the world's only maker of commercial extreme ultraviolet lithography (EUV) machines, a critical tool for chipmakers such as ‌Taiwan Semiconductor Manufacturing Co, Intel and others in producing advanced computing chips.

"It's not a parlor trick or something like this, where we demonstrate for a very short time that it can work," Michael Purvis, ASML's lead technologist for its EUV source light, said in an interview.

"It's a system that can produce 1,000 watts under all the same requirements that you could see at a customer," he added, speaking at the company's California facilities near San Diego.

MACHINES CRITICAL TO CHIP PRODUCTION

The EUV machines are so critical to chip production that U.S. governments of both parties have worked with Dutch leaders to prevent them from being shipped to China, spurring it to launch a national effort to build machines of its own.

In the United States, at least ‌two startups, Substrate and xLight, have raised hundreds of millions ⁠of dollars to develop American competitors to ASML's technology, with xLight securing government funding from President Donald Trump's administration.

With the technological advance revealed on Monday, which is being reported here for the first time, ASML aims to outdistance any would-be rivals by improving the most ⁠technologically challenging aspect of the machines.

This is the quest to generate EUV light with the right power and properties to turn out chips at high volume. The company's researchers have found a way to boost the power of the EUV light source to 1,000 watts from 600 watts now.

The chief advantage is that greater power translates into the ability to make more chips every hour, helping to lower the cost of each.

Chips are printed similar to a photograph, where the EUV light is shone on a silicon wafer coated with ‌special chemicals called a photoresist. With a more powerful EUV light source, chip factories need shorter exposure times.

"We'd like to make sure that our customers can keep on using EUV at a much lower cost," Teun van Gogh, executive vice president for the NXE line of EUV machines at ASML, told Reuters.

MACHINES COULD PROCESS 330 WAFERS AN HOUR BY 2030

Van Gogh said customers should be able to process about 330 silicon wafers an hour on each machine by the end of the decade, up from 220 now. Depending on the size of a chip, each wafer can hold anywhere from scores to thousands of the devices.
ASML got the power boost by doubling down on an approach ‌that already places its machines among the most complex inventions of humans.

To produce light with a wavelength of 13.5 nanometers, ASML's machine shoots a stream of molten droplets of tin through a chamber, where a massive carbon dioxide laser heats them into plasma.

This is a superheated state of matter in which the tin droplets become hotter than the sun and emit EUV light, to be collected by precision ‌optic equipment supplied by Germany's Carl Zeiss AG and fed into the machine to print chips.

The key advancements in Monday's disclosure involved doubling the number of tin drops to about 100,000 every second, and shaping them into plasma using two smaller laser bursts, as opposed to today's machines that use a single shaping burst.

"It's very challenging, because you need to master many things, many technologies," said Jorge J. Rocca, a professor at Colorado State University whose lab focuses on laser ‌technologies and has trained several ASML scientists.

"What was achieved - one kilowatt - is pretty amazing."

ASML believes the techniques it used to hit 1,000 watts will unlock continued advances in the future, Purvis said, adding, "We see a reasonably clear path toward 1,500 watts, and no fundamental reason why we couldn't get to 2,000 watts."

 
The key advancements in Monday's disclosure involved doubling the number of tin drops to about 100,000 every second, and shaping them into plasma using two smaller laser bursts, as opposed to today's machines that use a single shaping burst.
Mainstream media not understanding what they're talking about, right?

ASML's current machines already use two bursts, a low power one to shape each droplet into something disk like, and what has to be a favorable orientation for the first mirror, then a high power one to ionize the tin atoms, which then emit an EUV spectrum as the electrons drop back to lower energy orbits.

So besides brute force to increase even more the droplet rate, the high NA generation has an increase from the first, they've achieved higher useful EUV output with a more favorable shape and perhaps orientation.
 
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Mainstream media not understanding what they're talking about, right?

ASML's current machines already use two bursts, a low power one to shape each droplet into something disk like, and what has to be a favorable orientation for the first mirror, then a high power one to ionize the tin atoms, which then emit an EUV spectrum as the electrons drop back to lower energy orbits.

So besides brute force to increase even more the droplet rate, the high NA generation has an increase from the first, they've achieved higher useful EUV output with a more favorable shape and perhaps orientation.

In fact, in the new high-power sources ASML uses a 3-pulse sequence, first a 1 um flattening pulse, then a 1 um pre-pulse, followed by the 10 um main pulse; see also here:

https://semiwiki.com/forum/threads/asml’s-breakthrough-3-pulse-euv-light-source.22703/
 
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Exactly, Fred. The 1,000W milestone is monumental for throughput, but I’m curious how the industry plans to manage the localized thermal-mechanical stress at the 2nm node during these high-exposure bursts.

If we are doubling tin droplet rates to hit 330 wph, aren't we essentially creating a 'Heat Storm' that reactive throttling can't keep up with? It seems like yield recovery will become the primary bottleneck for 2026 tape-outs if we don't move toward more deterministic, proactive logic intercepts.

Has anyone seen data on how the GAA (Gate-All-Around) structures are holding up under these specific power levels, or are we still relying on standard emergency shutdown pins to prevent warpage?
 
How will the pellicle and the mask standup to this increased amount of power?

If the materials are not in lockstep, then what is the point?

It seems a lot of research into carbon nanotube (CNT) pellicles that seem (in principle) to have higher power limits, see eg here:

https://globaltechresearch.substack.com/p/carbon-nanotube-cnt-the-next-big
Some might question whether CNT pellicles will actually be widely adopted in the future, given the fact that the current EUV pellicle usage case is quite limited. Not only do memory manufacturers not use EUV pellicles, but even TSMC tries not to use EUV pellicles too much in their advanced node process, due to their high cost (over $10,000 per piece) and short lifespan (typically each need to be replaced every 3–4 days).

However, based on my supply chain research, TSMC plans to use CNT pellicles for its N2 process. If N2 mass production proves successful, CNT pellicles will be widely adopted in their A16 process. In the following paragraphs, I will explain why TSMC, previously hesitant to adopt EUV pellicles, is now actively embracing CNT pellicles, along with market size estimates and the qualification progress of each CNT pellicle manufacturers.


July 2025:
https://www.spiedigitallibrary.org/...pects-of-CNT-pellicle/10.1117/12.3072193.full

Feb 2026:
https://spie.org/advanced-lithograp...nsmission-of-CNT-based-pellicles-for/13979-46
 
It seems a lot of research into carbon nanotube (CNT) pellicles that seem (in principle) to have higher power limits, see eg here:

https://globaltechresearch.substack.com/p/carbon-nanotube-cnt-the-next-big
Some might question whether CNT pellicles will actually be widely adopted in the future, given the fact that the current EUV pellicle usage case is quite limited. Not only do memory manufacturers not use EUV pellicles, but even TSMC tries not to use EUV pellicles too much in their advanced node process, due to their high cost (over $10,000 per piece) and short lifespan (typically each need to be replaced every 3–4 days).

However, based on my supply chain research, TSMC plans to use CNT pellicles for its N2 process. If N2 mass production proves successful, CNT pellicles will be widely adopted in their A16 process. In the following paragraphs, I will explain why TSMC, previously hesitant to adopt EUV pellicles, is now actively embracing CNT pellicles, along with market size estimates and the qualification progress of each CNT pellicle manufacturers.


July 2025:
https://www.spiedigitallibrary.org/...pects-of-CNT-pellicle/10.1117/12.3072193.full

Feb 2026:
https://spie.org/advanced-lithograp...nsmission-of-CNT-based-pellicles-for/13979-46

That explain why the Foundry apply own pellicles if required!

That cost and usage cycletime a bit much for maskshop to deliver best service
 
Good point. With these power levels, pellicle lifetime and mask cycle time are now constrained economically, as well as technically. It is only logical that foundries are inclined to internal or node-specific pellicle policies in which EUV use is inevitable. With increasing EUV power, the source, pellicle material, resist, and mask handling flow will be co-optimized, as opposed to peak watts.
Semiconductor technology
 
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