Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/threads/dram-hbm-supply-demand-balance.25208/page-2
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/EmailDomainReplace] => 1000010
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2031070
            [XFI] => 1060170
        )

    [wordpress] => /var/www/html
)

DRAM/HBM supply-demand balance

So the next inflection point (with respect to supply) will be 3D DRAM?


But is 70% floor margin will exceed intel's hay day margin of low 60% when they had total domination.

I think they can hold that for the next few years because new fabs take a long time to build and since everyone underestimated this AI wave, there is now an air pocket. More importantly, people are not fully convinced that this surge will sustain (hence the SCAs, right?) so they will only cautiously invest capital.

But if this AI thing proves to be structural, then 70% GM floor will not hold; JVs or Chinese, there will be many more players.
Intel could re-enter the memory business if it really wanted to. Compared with 18A, DRAM is arguably much less complex from an execution standpoint—and it could potentially bring 70%+ margins while putting idle fabs to use.
The main hurdle would be IP, but even that could be addressed through licensing deals with players like Nanya or YMTC.

 
Intel could re-enter the memory business if it really wanted to. Compared with 18A, DRAM is arguably much less complex from an execution standpoint—and it could potentially bring 70%+ margins while putting idle fabs to use.
The main hurdle would be IP, but even that could be addressed through licensing deals with players like Nanya or YMTC.
DRAM would require substantially new process development and it is also an expensive process. In their recent collaboration with SAIMEMORY, they didn't provide the DRAM but the packaging technology.
 
DRAM would require substantially new process development and it is also an expensive process. In their recent collaboration with SAIMEMORY, they didn't provide the DRAM but the packaging technology.
Compared with 18A, this is almost straightforward. The bigger challenge is that Lip-Bu Tan may not be deeply familiar with the process side of memory. Hopefully, someone like Lee from SK could provide some guidance and help close that gap.
 
It's just a piece of cake compared with 18A. Only problem is LB tan is not familiar with the process. hopefully Lee from SK could give him some tutoring.
Oh it's hardly a piece of cake. Transistor structure is all different. High aspect ratio capacitor. You can only get good margins from reuse of modules.

Reviving 3D XPoint might be easier and better timing.
 
Last edited:
Oh it's hardly a piece of cake. Transistor structure is all different. High aspect ratio capacitor. You can only get good margins from reuse of modules.

Reviving 3D XPoint might be easier and better timing.

It would be super easy for Intel to pick up NAND again. They still remember most of the parameters in their head. DRAM, for leading edge maybe a little tricky.

for CXMT level of tech , not challenging at all.

1) Core architecture difference (this drives everything)​

[table]
[TR]
[th]Aspect[/th][th]Intel 18A (Logic)[/th][th]Leading DRAM[/th]
[/TR]
[TR]
[td]Device type[/td][td]CMOS logic (billions of transistors)[/td][td]1T1C memory cell (1 transistor + 1 capacitor)[/td]
[/TR]
[TR]
[td]Key innovation[/td][td]RibbonFET (GAA) + PowerVia backside power[/td][td]Buried wordline + high-aspect-ratio capacitor[/td]
[/TR]
[TR]
[td]Scaling driver[/td][td]Transistor electrostatics + interconnect[/td][td]Cell size + capacitor charge retention[/td]
[/TR]
[TR]
[td]Layout complexity[/td][td]Extremely heterogeneous (CPU, GPU, SRAM, analog)[/td][td]Highly repetitive array + simple periphery[/td]
[/TR]
[/table]
👉 DRAM is structurally simpler but process-specialized, while logic is architecturally complex + integration-heavy. [semiconductorx.com]

⚙️ 2) Process complexity comparison​

✅ Intel 18A (cutting-edge logic)​

  • Uses Gate-All-Around (RibbonFET) → full channel wrap for electrostatics [ofzenandco...puting.com]
  • Introduces PowerVia backside power delivery (first in HVM) [intel.com]
  • Heavy EUV / High-NA EUV usage
  • Complex interconnect stack (10–15+ metal layers typical)
  • Advanced DTCO + library tuning
➡️ Key reality:
  • Logic scaling = system-level co-optimization problem
  • Transistor + interconnect + power + thermal all coupled

✅ Leading DRAM (1α → 1γ)​

  • Uses:
    • Buried Wordline (BWL) transistor (recessed gate)
    • Capacitor-over-bitline (COB) storage
  • Capacitor aspect ratio >50:1 (very extreme etch/deposition) [semiconductorx.com]
  • Two process zones:
    • Memory array (specialized)
    • Periphery (logic-like CMOS)
➡️ Key reality:
  • DRAM complexity is process-specific, not architecture-wide
  • The hardest parts are:
    • Capacitor formation
    • Cell leakage / retention control

✅ Bottom line on complexity​

  • 18A: broad + systemic complexity (hard integration problem)
  • DRAM: narrow but deep complexity (hard materials/process problem)
👉 Your intuition is partly right:
  • DRAM avoids many logic headaches (routing, PPA tuning, variability)
  • But its high-aspect capacitor + scaling physics are equally brutal in their own domain

💰 3) Capex and cost comparison​

🏭 Fab construction​

[table]
[TR]
[th]Metric[/th][th]Advanced Logic Fab (18A-class)[/th][th]DRAM Fab[/th]
[/TR]
[TR]
[td]Typical cost[/td][td]$15B–$20B[/td][td]~$10B–$15B (varies, often lower)[/td]
[/TR]
[TR]
[td]Main driver[/td][td]EUV + extreme tool count[/td][td]Deposition / etch + some EUV[/td]
[/TR]
[TR]
[td]Tool cost (EUV)[/td][td]$150M–$350M per scanner[/td][td]Fewer layers → fewer tools[/td]
[/TR]
[/table]
[patentpc.com], [linkedin.com]
👉 Logic fabs are generally more capital-intensive due to:
  • More EUV layers
  • More masks
  • Higher process variability control requirements

💵 Wafer cost​

[table]
[TR]
[th]Node[/th][th]Logic wafer[/th][th]DRAM wafer (typical)[/th]
[/TR]
[TR]
[td]Leading edge[/td][td]~$17k–$22k (3nm class)[/td][td]Usually lower (fewer EUV layers)[/td]
[/TR]
[/table]
[siliconanalysts.com]
👉 Logic wafers are more expensive due to:
  • EUV intensity
  • Multi-patterning and tighter tolerances

📈 Cost structure difference​

Logic (18A)
  • High NRE (design + masks)
  • High wafer cost
  • Lower volume per design
DRAM
  • Lower design cost (high reuse)
  • Massive volume scaling
  • Profitability driven by yield + cycle timing

🧪 4) Process steps & flow differences​

[table]
[TR]
[th]Factor[/th][th]18A Logic[/th][th]DRAM[/th]
[/TR]
[TR]
[td]Lithography layers[/td][td]Very high (EUV-heavy)[/td][td]Moderate[/td]
[/TR]
[TR]
[td]Etch/deposition intensity[/td][td]Balanced[/td][td]Extreme (capacitor + trench)[/td]
[/TR]
[TR]
[td]Process steps[/td][td]1000–1500+[/td][td]Slightly fewer but specialized[/td]
[/TR]
[TR]
[td]Variability sensitivity[/td][td]Ultra high (timing-critical)[/td][td]High (retention + leakage)[/td]
[/TR]
[TR]
[td]Yield challenge[/td][td]Design + process interaction[/td][td]Defect density + capacitor uniformity[/td]
[/TR]
[/table]

🧩 5) Talent & know-how barrier​

This is where your earlier point actually matters a lot:

Logic (18A)​

  • Requires:
    • DTCO experts
    • advanced device physics (GAA)
    • system-level integration

DRAM​

  • Requires:
    • materials science + capacitor engineering
    • deep process recipe know-how
    • yield learning accumulated over decades
👉 DRAM is not easily “re-enterable” because:
  • Know-how is tacit (Samsung / SK / Micron advantage)
  • Process IP is deeply embedded in fab recipes

⚖️ 6) Strategic conclusion​

✔ Where you’re right​

  • DRAM does not require bleeding-edge logic architecture innovation
  • It can utilize existing fabs more efficiently
  • Margins can be very strong in upcycles (especially HBM)

❗ Where reality is tougher​

  • DRAM is not “easy” vs 18A, just different complexity
  • IP + process integration know-how is a huge barrier
  • Industry is effectively an oligopoly (Samsung / SK / Micron) [semiconductorx.com]

🧠 Final takeaway​

  • 18A = peak integration complexity + highest capex
  • DRAM = extreme process specialization + entrenched incumbents
👉 In simple terms:
  • Logic is hard to build
  • DRAM is hard to master
 

Amid market chatter that big tech firms are reportedly evaluating Chinese memory products, Micron, during its earnings call, acknowledged the country’s progress in memory development. South China Morning Post, citing Micron Chief Business Officer Sumit Sadana, reports that both CXMT and YMTC have steadily improved their capabilities and expanded market share over time.

The remarks, as per the report, underscore a degree of global validation for China’s memory sector at a time when surging AI infrastructure investment is reshaping an industry historically marked by cyclical booms and downturns.

However, Sadana also noted that the “overwhelming majority” of their output remains sold domestically in China, the report suggests.

South China Morning Post points out that while Chinese suppliers still lag behind Micron and its Korean peers in HBM, Micron executives highlighted tightening supply conditions in non-HBM segments, suggesting potential upside for China’s major DRAM maker, whose product mix remains concentrated in mainstream LPDDR and DDR DRAM.

Meanwhile, South Korea is also closely watching the development. A separate report from Kyunghyang Shinmun, citing Professor Lee Jong-hwan of Sangmyung University, estimates the technology gap between Korea and China at around 2–3 years in general-purpose DRAM and NAND, and over five years in HBM, though the gap is gradually narrowing.
 

Amid market chatter that big tech firms are reportedly evaluating Chinese memory products, Micron, during its earnings call, acknowledged the country’s progress in memory development. South China Morning Post, citing Micron Chief Business Officer Sumit Sadana, reports that both CXMT and YMTC have steadily improved their capabilities and expanded market share over time.

The remarks, as per the report, underscore a degree of global validation for China’s memory sector at a time when surging AI infrastructure investment is reshaping an industry historically marked by cyclical booms and downturns.

However, Sadana also noted that the “overwhelming majority” of their output remains sold domestically in China, the report suggests.

South China Morning Post points out that while Chinese suppliers still lag behind Micron and its Korean peers in HBM, Micron executives highlighted tightening supply conditions in non-HBM segments, suggesting potential upside for China’s major DRAM maker, whose product mix remains concentrated in mainstream LPDDR and DDR DRAM.

Meanwhile, South Korea is also closely watching the development. A separate report from Kyunghyang Shinmun, citing Professor Lee Jong-hwan of Sangmyung University, estimates the technology gap between Korea and China at around 2–3 years in general-purpose DRAM and NAND, and over five years in HBM, though the gap is gradually narrowing.
We also shouldn’t underestimate the potential acceleration they could get from the significant capital available now. In previous years, profitability was limited, and the business wasn’t particularly attractive to top graduates. With stronger financial backing and renewed momentum, that dynamic could change quite quickly.
 
One point I think is still underestimated is that HBM supply is constrained by much more than DRAM wafer capacity. Even if memory makers decide to expand wafer starts aggressively, they still need advanced packaging, known-good-die yield, TSV processing, thermal validation and GPU qualification to scale at the same pace. These are coupled bottlenecks rather than independent ones. In other words, adding wafer capacity alone does not translate into proportional HBM bit output. The entire manufacturing chain has to scale together, which makes the supply response much slower than many traditional DRAM cycle models assume.
 
Back
Top