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I understand that denser DRAM spends more time refreshing than 'less dense DRAM', in terms of operating time (read/write) vs. refresh time. Example: a 64GB DIMM can be expected to 'lose more bandwidth waiting for refresh' than a 32GB or 16GB DIMM.
Does this increasing refresh time with density present a limit on how densely we can scale DRAM? .. or is this something that gets worked around with finer granularity on refresh timing, or other tricks in the future?
(I also assume 3D DRAM isn't really phased by this since each stack will potentially refresh at the same time - reducing the # of rows/cycles that must refresh at once, per GB size).
It isn't the long pole in the DRAM scaling equation but it's certainly an important consideration. Embedded DRAM (IBM) was/is big with gaming consoles because it allows developers to work around the Von Neumann bottleneck, but it's a monkey's paw situation. The larger thermal budget required to manufacture the bitcells degrades performance monolithically, so its digital can never be as efficient as a baremetal equivalent in a pure digital process. It cuts the other way too because compromises have to be made in the bitcell to maintain viable digital performance - e.g. embedded DRAM has a comically bad refresh rate that makes no sense to anyone outside of niche applications that are willing to deal with it. A 1F^2 bitcell would be the next noticable improvement to DRAM, but certainly you would need more ranks, smarter memory controllers, array architectures, etc. to work around the refresh thing, but that's all downstream of developing a 1F^2 bitcell which is the trickiest, albiet most compelling part of the problem (see Optane boondoggle).
For DDR5/LPDDR5, refresh rate doubled from every 64 ms to every 32 ms. I'm pretty sure rowhammer had a lot to do with it. So this basically affects 1b onwards, although the issues started as early as 2x nm I'm sure.
Does this increasing refresh time with density present a limit on how densely we can scale DRAM? .. or is this something that gets worked around with finer granularity on refresh timing, or other tricks in the future?
The scaling will be most strongly impacted by distances within the DRAM cell itself. The VCT 4F2 architecture is motivated by the bit line approaching the capacitor active area contact too closely, while the 3D DRAM architecture comes from the capacitor itself becoming too thin.
(I also assume 3D DRAM isn't really phased by this since each stack will potentially refresh at the same time - reducing the # of rows/cycles that must refresh at once, per GB size).
The 3D DRAM in principle reduces the rowhammer risk with larger separations between word lines, but the JEDEC standard of 32 ms may be locked in at that time. The refresh rate is not that high a priority for scaling.
