This quarterly newsletter provides you with the latest information on DesignWare[SUP]®[/SUP] IP including in-depth technical articles, whitepapers, videos, webinars and more. You can read this newsletter online.
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| style="font-family: arial; font-size: 16pt; padding-top: 10px" | Featured Articles
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| style="font-family: arial; font-size: 12px; padding-top: 10px" | Optimizing high-end embedded designs with the ARC HS Processor Family
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| style="font-family: arial; font-size: 11px" | The new DesignWare ARC HS processors deliver more than 4200 DMIPS per core at less than 80 mW of power consumption for high-end embedded applications.
|-
| style="font-family: arial; font-size: 12px; padding-top: 10px" | Demystifying 40 Gigabit Ethernet Interfaces in the Data Centers
|-
| style="font-family: arial; font-size: 11px" | Learn about the 40G networking system electrical interfaces (XLAUI, XLPPI and 40GBASE-KR4) and module form factors that enable a cost-effective migration to higher bandwidth and is deployable in today’s data centers.
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| style="font-family: arial; font-size: 12px; padding-top: 10px" | What’s new with DesignWare Building Blocks and minPower Components in I-2013.12?
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| style="font-family: arial; font-size: 11px" | Learn about DesignWare I-2013.12’s enhanced analyze_datapath_extraction command, new Saturation Multiplier and Saturation Divider, and minPower support for instantiated components in DC Explorer.
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| style="font-family: arial; font-size: 12px; padding-top: 10px" | Delivering on the Promise of Guaranteed Isochronous Traffic in USB 3.1
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| style="font-family: arial; font-size: 11px" | USB 3.1 allows 10 Gbps and 5 Gbps devices to coexist in the same topology. Learn about the protocol changes which guarantee the bandwidth and bounded latency of the isochronous transfer type in this mixed environment.
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| style="font-family: arial; font-size: 16pt; padding-top: 10px" | In-depth White Papers
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| [table] style="width: 100%"
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| align="left" valign="center" style="width: 30px" |
| valign="top" style="padding-bottom: 0px; padding-left: 0px; padding-right: 10px; font-family: arial; font-size: 12px; padding-top: 5px" | The Linley Group: Synopsys ARC HS Processors: High-Speed Licensable CPU Cores for Embedded Applications
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| align="left" valign="center" style="width: 30px" |
| valign="top" style="padding-bottom: 0px; padding-left: 0px; padding-right: 10px; font-family: arial; font-size: 12px; padding-top: 5px" | Reducing Power Consumption in Mobile Applications with High-Speed Gear3 MIPI M-PHY IP
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| align="left" valign="center" style="width: 30px" |
| valign="top" style="padding-bottom: 0px; padding-left: 0px; padding-right: 10px; font-family: arial; font-size: 12px; padding-top: 5px" | How HDMI 2.0 Will Enrich the Multimedia Experience
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| style="padding-bottom: 0px; padding-left: 0px; padding-right: 0px; font-family: arial; font-size: 16pt; padding-top: 10px" | On-Demand Webinars
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| [table] style="width: 100%"
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| align="left" valign="top" style="width: 30px" |
| valign="top" style="padding-bottom: 0px; padding-left: 0px; padding-right: 10px; font-family: arial; font-size: 12px; padding-top: 5px" | Optimizing High-End Embedded Designs with High-Performance Processors
|-
| align="left" valign="top" style="width: 30px" |
| valign="top" style="padding-bottom: 0px; padding-left: 0px; padding-right: 10px; font-family: arial; font-size: 12px; padding-top: 5px" | Putting the Smarts into Smart Things - Designing ICs for the Internet of Things
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| align="left" valign="top" style="width: 30px" |
| valign="top" style="padding-bottom: 0px; padding-left: 0px; padding-right: 10px; font-family: arial; font-size: 12px; padding-top: 5px" | Enterprise Ethernet IP for Data Center SoC Designs
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| align="left" valign="top" style="width: 30px" |
| valign="top" style="padding-bottom: 0px; padding-left: 0px; padding-right: 10px; font-family: arial; font-size: 12px; padding-top: 5px" | Reduce SoC Test Cost and Cut Weeks off Test Integration with Hierarchical Testing of all IP on a SoC
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[/table]
[table]
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| style="padding-bottom: 0px; padding-left: 0px; padding-right: 0px; font-family: arial; font-size: 16pt; padding-top: 10px" | Industry Articles
|-
| style="padding-bottom: 10px; padding-left: 0px; padding-right: 10px; font-family: arial; font-size: 12px; padding-top: 10px" | Insight: Solving the Power-Performance Paradox for High-End Embedded Processors
EDN: Optimizing High-Performance CPUs, GPUs and DSPs? Use Logic and Memory IP – Part I
Insight: Common Sense: New IP Subsystem Reduces Design Risk for SoC Sensor Integration
Insight: Mega Data Centers Drive Demand for a New Class of SoCs
Electronic Design: The 12 Tenets of the Low-Power Design Gospel
Insight: DesignWare ARC nSIM: Speed, Accuracy and Visibility – Instruction Set Simulation without Compromise!
Insight: Understanding HDMI 2.0: Enabling the Ultra-High Definition Experience
Insight: Scalable Architectures for Analog IP on Advanced Process Nodes
SemiWiki: Why Integrating HDMI 2.0?
Chip Design: USB 3.0 SSIC: Low-Power Interconnect for Mobile Consumer Applications
|-
[/table]
Check out the DesignWare Technical Bulletin online for additional information. Subscribe to the DesignWare Technical Bulletin to receive future issues.
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[table] style="width: 100%"
|-
| style="font-family: arial; font-size: 16pt; padding-top: 10px" | Featured Articles
|-
| style="font-family: arial; font-size: 12px; padding-top: 10px" | Optimizing high-end embedded designs with the ARC HS Processor Family
|-
| style="font-family: arial; font-size: 11px" | The new DesignWare ARC HS processors deliver more than 4200 DMIPS per core at less than 80 mW of power consumption for high-end embedded applications.
|-
| style="font-family: arial; font-size: 12px; padding-top: 10px" | Demystifying 40 Gigabit Ethernet Interfaces in the Data Centers
|-
| style="font-family: arial; font-size: 11px" | Learn about the 40G networking system electrical interfaces (XLAUI, XLPPI and 40GBASE-KR4) and module form factors that enable a cost-effective migration to higher bandwidth and is deployable in today’s data centers.
|-
| style="font-family: arial; font-size: 12px; padding-top: 10px" | What’s new with DesignWare Building Blocks and minPower Components in I-2013.12?
|-
| style="font-family: arial; font-size: 11px" | Learn about DesignWare I-2013.12’s enhanced analyze_datapath_extraction command, new Saturation Multiplier and Saturation Divider, and minPower support for instantiated components in DC Explorer.
|-
| style="font-family: arial; font-size: 12px; padding-top: 10px" | Delivering on the Promise of Guaranteed Isochronous Traffic in USB 3.1
|-
| style="font-family: arial; font-size: 11px" | USB 3.1 allows 10 Gbps and 5 Gbps devices to coexist in the same topology. Learn about the protocol changes which guarantee the bandwidth and bounded latency of the isochronous transfer type in this mixed environment.
|-
| style="font-family: arial; font-size: 16pt; padding-top: 10px" | In-depth White Papers
|-
| [table] style="width: 100%"
|-
| align="left" valign="center" style="width: 30px" |
| valign="top" style="padding-bottom: 0px; padding-left: 0px; padding-right: 10px; font-family: arial; font-size: 12px; padding-top: 5px" | The Linley Group: Synopsys ARC HS Processors: High-Speed Licensable CPU Cores for Embedded Applications
|-
| align="left" valign="center" style="width: 30px" |
| valign="top" style="padding-bottom: 0px; padding-left: 0px; padding-right: 10px; font-family: arial; font-size: 12px; padding-top: 5px" | Reducing Power Consumption in Mobile Applications with High-Speed Gear3 MIPI M-PHY IP
|-
| align="left" valign="center" style="width: 30px" |
| valign="top" style="padding-bottom: 0px; padding-left: 0px; padding-right: 10px; font-family: arial; font-size: 12px; padding-top: 5px" | How HDMI 2.0 Will Enrich the Multimedia Experience
|-
[/table]
|-
| style="padding-bottom: 0px; padding-left: 0px; padding-right: 0px; font-family: arial; font-size: 16pt; padding-top: 10px" | On-Demand Webinars
|-
| [table] style="width: 100%"
|-
| align="left" valign="top" style="width: 30px" |
| valign="top" style="padding-bottom: 0px; padding-left: 0px; padding-right: 10px; font-family: arial; font-size: 12px; padding-top: 5px" | Optimizing High-End Embedded Designs with High-Performance Processors
|-
| align="left" valign="top" style="width: 30px" |
| valign="top" style="padding-bottom: 0px; padding-left: 0px; padding-right: 10px; font-family: arial; font-size: 12px; padding-top: 5px" | Putting the Smarts into Smart Things - Designing ICs for the Internet of Things
|-
| align="left" valign="top" style="width: 30px" |
| valign="top" style="padding-bottom: 0px; padding-left: 0px; padding-right: 10px; font-family: arial; font-size: 12px; padding-top: 5px" | Enterprise Ethernet IP for Data Center SoC Designs
|-
| align="left" valign="top" style="width: 30px" |
| valign="top" style="padding-bottom: 0px; padding-left: 0px; padding-right: 10px; font-family: arial; font-size: 12px; padding-top: 5px" | Reduce SoC Test Cost and Cut Weeks off Test Integration with Hierarchical Testing of all IP on a SoC
|-
[/table]
|-
[/table]
[table]
|-
| style="padding-bottom: 0px; padding-left: 0px; padding-right: 0px; font-family: arial; font-size: 16pt; padding-top: 10px" | Industry Articles
|-
| style="padding-bottom: 10px; padding-left: 0px; padding-right: 10px; font-family: arial; font-size: 12px; padding-top: 10px" | Insight: Solving the Power-Performance Paradox for High-End Embedded Processors
EDN: Optimizing High-Performance CPUs, GPUs and DSPs? Use Logic and Memory IP – Part I
Insight: Common Sense: New IP Subsystem Reduces Design Risk for SoC Sensor Integration
Insight: Mega Data Centers Drive Demand for a New Class of SoCs
Electronic Design: The 12 Tenets of the Low-Power Design Gospel
Insight: DesignWare ARC nSIM: Speed, Accuracy and Visibility – Instruction Set Simulation without Compromise!
Insight: Understanding HDMI 2.0: Enabling the Ultra-High Definition Experience
Insight: Scalable Architectures for Analog IP on Advanced Process Nodes
SemiWiki: Why Integrating HDMI 2.0?
Chip Design: USB 3.0 SSIC: Low-Power Interconnect for Mobile Consumer Applications
|-
[/table]
Check out the DesignWare Technical Bulletin online for additional information. Subscribe to the DesignWare Technical Bulletin to receive future issues.
<script src="//platform.linkedin.com/in.js" type="text/javascript">
lang: en_US
</script>
<script type="IN/Share" data-counter="right"></script>