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Darth Vader in Semiconductor Industry?How the Turncoat and the Loyalist of TSMC Shaped the Global Chip War

Jin Chen

New member
Liang Mong-song(梁孟松),former heroes in the semiconductor industry, who would eventually be seen in Taiwan as a traitor by later working for Samsung Electronics and then becoming co-CEO of Chinese chipmaker SMIC.

Eeven with a ban on EUV equipment sales, SMIC under his leadership managed to mass-produce 7nm chips and is now advancing toward 5nm, stunning the world. He is increasingly seen as the “Darth Vader of the semiconductor industry.”

In 2005, when Chang chose Rick Tsai to succeed him as CEO. There was a major reshuffle of TSMC’s management, and as part of that shake-up, Liang expected to be promoted to the key role of R&D vice president. Instead, he was passed over, leaving him furious.

He jumped to arch-rival Samsung to become chief technology officer for the Korean company’s wafer foundry business, and helped Samsung surge ahead of TSMC on 14nm semiconductor production.

Suspecting Liang of foul play, TSMC sued him for leaking trade secrets.

It was still surprising, however, that just two years later, he would leave Korea and go to China, where he had emerged as a key figure in the technology war between Washington and Beijing.

Chinese information and communications giant Huawei shocked the world in 2023 when it apparently got around American sanctions and used an advanced 7nm chip in its newest flagship smartphone. Although Huawei never admitted the chip was made by SMIC, industry insiders strongly suspected that Liang was the “shadow warrior” behind the breakthrough.

Why is Liang so obsessed with his former company?

(Continue reading the full story on Tech Taiwan Substack.)
 
Eeven with a ban on EUV equipment sales, SMIC under his leadership managed to mass-produce 7nm chips and is now advancing toward 5nm, stunning the world. He is increasingly seen as the “Darth Vader of the semiconductor industry.”
Not sure why mass producing 7nm chips without EUV is seen as impressive. Intel 7 was also done without EUV, unless I missed something somewhere. In any event, this is still 2 nodes behind the leading edge.
 
Not sure why mass producing 7nm chips without EUV is seen as impressive. Intel 7 was also done without EUV, unless I missed something somewhere. In any event, this is still 2 nodes behind the leading edge.
I've also read the original TSMC N7 variant was DUV only. Could you/someone here confirm that? Was Zen 3 built on the DUV 7nm process? Just curious.
 
I've also read the original TSMC N7 variant was DUV only. Could you/someone here confirm that? Was Zen 3 built on the DUV 7nm process? Just curious.
N7 was DUV-only. N7+ introduced some EUV layers, but wasn't a success because the design rules were incompatible with N7 so no easy IP portability.
 
Liang saw the transfer as an insult. “Being reassigned to a unit with an extremely small budget and outdated technology was clearly a ‘demotion,’ and could in no uncertain terms be called ‘being given an important responsibility,’” he said at his trade-secrets trial, according to court records.

From everyone familiar, I heard that Liang's departure had nothing else to do with anything, but money, and TSMC higher ups spread that "ambition" spin out of embarrassment. For Liang to play to it, would also be very beneficial to raise the price for his services. He says different things to Taiwanese, and mainlanders on why he left.

To me that sounds very realistic.
 
From managing the most cutting-edge technologies, Liang was reassigned to a new venture called “More than Moore” that would take TSMC’s mature processes and convert them into new products such as automotive chips and image sensors.

That would've been pretty much a dream job these days as the prices for legacy processes went skyhigh during covid, I see so much money being buried in old fabs with a lot of captive clients.

I myself would've liked to experiment with "old node refresh", and trying to squeeze more from last dry litho, and last single patterning nodes more with minor tool refresh to more modern, and higher performance ones, and optimised design rules, and cells + all the semiconductor material science knowledge the industry has gotten over the last 10-15 years since 40-65-90 nodes debuted.

I believe there is still is a lot of reserve of device performance, and tool performance left to be squeezed from them, with new interesting commercial spins possible like very fast, low MOQ tape outs.
 
That would've been pretty much a dream job these days as the prices for legacy processes went skyhigh during covid, I see so much money being buried in old fabs with a lot of captive clients.

I myself would've liked to experiment with "old node refresh", and trying to squeeze more from last dry litho, and last single patterning nodes more with minor tool refresh to more modern, and higher performance ones, and optimised design rules, and cells + all the semiconductor material science knowledge the industry has gotten over the last 10-15 years since 40-65-90 nodes debuted.

I believe there is still is a lot of reserve of device performance, and tool performance left to be squeezed from them, with new interesting commercial spins possible like very fast, low MOQ tape outs.

Mask Shops also appreciate FABS getting the max out of the old nodes!!!
 
Mask Shops also appreciate FABS getting the max out of the old nodes!!!

Masks are cheap on the old nodes, and fast which is good, and you likely get your first mask set without defects on the first try.

But the fun starts when you get to companies with very old designs for which they don't have digital design files, but only a physical mask set, which has to be kept in immaculate condition. Or ones which use some tricky ancient multiple exposure mask ROMs system.

There are few "levels" on which a legacy node refresh is possible:
  • 1. Complete mask-compatible drop-in. You just get newer, faster, better tools, while litho, and device design stays as is.
  • 2. Process change requiring new masks, and design rules changes: better metal, newer etch/deposition/thermal processes, introducing inverse lithographic techniques on older nodes, but underlying device design stays as is
  • 3. Deep refresh, which is essentially a new node, with old litho tools: here you can "back-port" much more from newer nodes to older ones, and you exploit new margins given by newer tools for more density, and performance. For example, adding metal gates to older nodes, and new cell designs.
 
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