Contamination Levels for future CMOS processing?

[BTyndall]

With continued scaling from 10nm to 7nm and beyond (ITRS 2.0 has nano-wire diameter for GAA devices set at 5nm for the foreseeable future) how will contamination specification for safe and reliable processing evolve?

That is, as dimensions reduce will contamination tolerances tighten? Or are current specifications suitable for the immediate future?

This will depend on the nature of the contamination source, whether its particulates, metals, molecular or airborne contamination but in general is there a potential show stopper or concern either from a economic or device physics point of view?

Thanks in advance!