Focus of Seven Papers and Posters Includes Hybrid Bonding And Low-Temperature Processing.
GRENOBLE, France – April 28, 2026 – CEA-Leti will present seven papers and posters on technologies shaping the next decade of advanced heterogenous integration at the Electronic Components and Technology Conference (ECTC) May 26-29 in Orlando, Fla.
These developments cover a variety of technologies, including reducing interconnect pitches through hybrid bonding interconnection, for low-temperature processes, superconducting interconnects and fan-out wafer-level packaging.
Hybrid bonding, which is based on direct copper-to-copper and dielectric-to-dielectric connection technology, enables ultra-fine pitch vertical interconnects. It is emerging as the primary path for high-density 3D integration, as micro-bump approaches reach their scaling limits.
For example, in the paper “Die-To-Wafer Hybrid Bonding Technology down to 1 μm pitch for Multi-Die Stacking Integration" CEA-Leti will present its first demonstration of a die-to-wafer hybrid bonding test vehicle with a pitch as small as 1µm.
Low-temperature processing enables heterogeneous integration in which temperature-sensitive materials (polymers, certain semiconductors) must coexist with standard CMOS processes. The ability to form robust interconnects below typical thermal budgets opens pathways for stacking previously incompatible technologies. The first time successful direct hybrid bonding annealed at ultra-low temperatures down to 100 °C will be presented.
As transistor gate-scaling slows, system-level integration through advanced packaging delivers the performance, power, and form-factor improvements that end-users expect. CEA-Leti's research on hybrid bonding that will be presented at ECTC 2026 reflects growing industry alignment around hybrid bonding as a key enabler of next-generation, high-performance packaging.
Specialized Applications
Beyond foundational process development, CEA-Leti researchers will also present application-specific integration advances:
- Quantum Systems: The superconducting 3D interconnect work signals packaging infrastructure development for quantum computing, where thermal resistance and electromagnetic isolation are significant constraints.
- RF/Wireless: The RADAR system-in-package with integrated antennas demonstrates continued innovation in fan-out wafer-level packaging for millimeter-wave applications, critical for 5G/6G and automotive radar.
Papers & Posters
“Hybrid Bonding with Ultra-Low Temperature Annealing: Morphological and Electrical Validations"
Author: Margot Faure
Session 3
Wednesday, May 27 from 9:30 AM – 9:50 AM
“Enabling Low-Temperature Fine-Pitch Hybrid Bonding: Role of Nanocrystalline Copper Microstructures and Pre-Bond Surface Treatments"
Session 3
Author: Mathieu Loyer (in collaboration with STMicroelectronics)
Wednesday, May 27 from 11:35 AM – 11:55 AM
“RADAR System-in-Package with Integrated Antennas based on Fan-Out Wafer-Level Packaging RDL-First"
Session 39 (Poster)
Author: Arnaud Garnier
Wednesday, May 27 from 2:30 PM – 4:30 PM
“Electroplated Indium Micro-Bumps: Toward Scalable Low Temperature Ultra-Fine Pitch Interconnects"
Session 40
Author: Maria-Luisa Calvo-Munoz
Wednesday, May 27 from 4:45 PM – 5:05 PM
“Impact of Copper Density on Via-to-Via Hybrid Bonding: Morphological and Electrical Characterizations"
Session 39 (Poster)
Author: Agathe Lerat
Thursday, May 28 from 10:00 AM – 12:00 PM
“Fine-Pitch Thermally Resistive Superconducting 3D Interconnects for Quantum Systems"
Session 39, (Poster)
Author: Pablo Renaud
Thursday, May 28 from 10:00 AM – 12:00 PM
“Die-To-Wafer Hybrid Bonding Technology down to 1 μm pitch for Multi-Die Stacking Integration"
Session 31
Author: Melissa Najem
Friday, May 29 from 2:00 PM – 2:20 PM
Link to Press Release