Daniel Payne
Moderator
The March 10-11, 2015 proceedings are available now:
[table] cellpadding="4" align="center" style="width: 100%"
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| align="left" valign="top" style="width: 80%" | Session CUS101 : Layout Challanges and Solutions for 14nm FinFET
GLOBALFOUNDRIES
|-
| valign="top" style="width: 2%" | Session CUS102 : Rapid Analog Prototyping for Circuit Designers
Analog Devices
|-
| valign="top" style="width: 2%" | Session CUS103 : Custom Layout Methodologies with Virtuoso Advanced Node
Samsung
|-
| width="2%" valign="top" style="font-family: Arial, Helvetica; background-color: transparent" | Session CUS104 : Verifying 16nm FinFET design with Spectre APS and Virtuoso ADE
Xilinx
|-
| width="2%" valign="top" style="font-family: Arial, Helvetica; background-color: transparent" | Session CUS105 : Should You Use the Layout Dependent Effect (LDE) Flow? It Depends. An Initial Evaluation of Cadence LDE flow for 16nm
Freescale Semiconductor
|-
| width="2%" valign="top" style="font-family: Arial, Helvetica; background-color: transparent" | Session CUS201 : 55LPX Process Electrically Aware Design Flow
GLOBALFOUNDRIES
|-
| width="2%" valign="top" style="font-family: Arial, Helvetica; background-color: transparent" | Session CUS202 : Optimizing ADE/ADE XL Spectre APS and AMS Designer Simulations with Limited Resources
Skyworks Solutions
|-
| width="2%" valign="top" style="font-family: Arial, Helvetica; background-color: transparent" | Session CUS203 : Multi-Site Design and IP Management Best Practices & Technologies
IC Manage
|-
| width="2%" valign="top" style="font-family: Arial, Helvetica; background-color: transparent" | Session CUS205 : Early Detection of Layout Induced Stress Effect in 28nm UMC Process Technology
Cadence
|-
| width="2%" valign="top" style="font-family: Arial, Helvetica; background-color: transparent" | Session CUS206 : Robust, High-Frequency Circuit Design Using Cadence EAD
Microchip Technology
|-
| width="2%" valign="top" style="font-family: Arial, Helvetica; background-color: transparent" | Session CUS207 : Library Based Implementation of a Buck Converter Model for Top Down Analog Design
Dialog Semiconductor
|-
[/table]
[table] cellpadding="4" align="center" style="width: 100%"
|-
| align="left" valign="top" style="width: 80%" | Session CUS101 : Layout Challanges and Solutions for 14nm FinFET
GLOBALFOUNDRIES
|-
| valign="top" style="width: 2%" | Session CUS102 : Rapid Analog Prototyping for Circuit Designers
Analog Devices
|-
| valign="top" style="width: 2%" | Session CUS103 : Custom Layout Methodologies with Virtuoso Advanced Node
Samsung
|-
| width="2%" valign="top" style="font-family: Arial, Helvetica; background-color: transparent" | Session CUS104 : Verifying 16nm FinFET design with Spectre APS and Virtuoso ADE
Xilinx
|-
| width="2%" valign="top" style="font-family: Arial, Helvetica; background-color: transparent" | Session CUS105 : Should You Use the Layout Dependent Effect (LDE) Flow? It Depends. An Initial Evaluation of Cadence LDE flow for 16nm
Freescale Semiconductor
|-
| width="2%" valign="top" style="font-family: Arial, Helvetica; background-color: transparent" | Session CUS201 : 55LPX Process Electrically Aware Design Flow
GLOBALFOUNDRIES
|-
| width="2%" valign="top" style="font-family: Arial, Helvetica; background-color: transparent" | Session CUS202 : Optimizing ADE/ADE XL Spectre APS and AMS Designer Simulations with Limited Resources
Skyworks Solutions
|-
| width="2%" valign="top" style="font-family: Arial, Helvetica; background-color: transparent" | Session CUS203 : Multi-Site Design and IP Management Best Practices & Technologies
IC Manage
|-
| width="2%" valign="top" style="font-family: Arial, Helvetica; background-color: transparent" | Session CUS205 : Early Detection of Layout Induced Stress Effect in 28nm UMC Process Technology
Cadence
|-
| width="2%" valign="top" style="font-family: Arial, Helvetica; background-color: transparent" | Session CUS206 : Robust, High-Frequency Circuit Design Using Cadence EAD
Microchip Technology
|-
| width="2%" valign="top" style="font-family: Arial, Helvetica; background-color: transparent" | Session CUS207 : Library Based Implementation of a Buck Converter Model for Top Down Analog Design
Dialog Semiconductor
|-
[/table]