BTC mining chips .
TSMC N3P and N2.
Can Intel recover even part of their past dominance?
- Thread starter Arthur Hanson
- Start date
TSMC N3P and N2.
interesting. i thought bit mining is mainly performance driven. Lowering vdd to 0.25v using existing leading edge means they are all doing sub-threhold computing?
N2 elvt threhold is around 0.1v.
The real trick is leakage.
Most btc mining chips are using dynamic logic which are almost impossible for elvt.
This is also why the latest btc miner requires an ambient temperature below 45 °C.
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thanks great info. For design point, BTC is not using higher Vdd due to overall power constraints? what was constraining it, DC cooling?
Electricity accounts 80% of BTC mining. You want to try everything to lower the power consumption
Beyond a given point, lowering voltage further increases power consumption per operation.
If you look at power-delay product, this tells you the energy needed to do something, Dynamic power (CV^2) drops with lower voltages (leakage less so) but so does clock speed, more rapidly as you get closer to the threshold voltages. For a given gate type (e.g. ELVT, ULVT, LVT, SVT) and clock speed (and activity percentage) there is a supply voltage where PDP reaches a minimum, and this where the power consumption is also a minimum -- as VDD drops you have to run slower but with more parallel circuits, which works for many things but not all. And if you're really bothered about power efficiency, you also need to vary VDD with process corner and temperature, and also circuit activity and clock speed.
For the circuits we've looked at in N3 and N2 which are relatively high activity (e.g. DSP, FEC...) the lowest PDP is usually with ELVT, but has never been as low as 0.225V -- for lower activity circuits where ELVT leakage is too high compared to dynamic power, ULVT can be better. But there's no single "best" answer (transistor type, voltage, frequency), it all depends on what the circuits are doing... ;-)
If you look at power-delay product, this tells you the energy needed to do something, Dynamic power (CV^2) drops with lower voltages (leakage less so) but so does clock speed, more rapidly as you get closer to the threshold voltages. For a given gate type (e.g. ELVT, ULVT, LVT, SVT) and clock speed (and activity percentage) there is a supply voltage where PDP reaches a minimum, and this where the power consumption is also a minimum -- as VDD drops you have to run slower but with more parallel circuits, which works for many things but not all. And if you're really bothered about power efficiency, you also need to vary VDD with process corner and temperature, and also circuit activity and clock speed.
For the circuits we've looked at in N3 and N2 which are relatively high activity (e.g. DSP, FEC...) the lowest PDP is usually with ELVT, but has never been as low as 0.225V -- for lower activity circuits where ELVT leakage is too high compared to dynamic power, ULVT can be better. But there's no single "best" answer (transistor type, voltage, frequency), it all depends on what the circuits are doing... ;-)
‘ Nvidia is the new Intel’. Is that a positive or negative remark?
siliconbruh999
Well-known member
maybe half of it