As an old time designer, I get the feeling that the tool chains expect bug free HDL input. Experience has shown that the first step in any design is to design the logic then use whatever tools that are available for physical design and that HDL is used to build the HW. The logic can then be mapped to either HW or SW so there is a need to model both on the same platform.
The modular classes in OOP are analogous to Verilog modules. Important features are that get/set access to class properties correspond to module input/output and assignment to variables corresponds to wire assignments in Verilog. The syntax differences can be handled by parsing source and generating different syntax. This is not C to Verilog -- it is using C to define the logic function and generating Verilog to express that same function.
I am using Visual Studio Express C# to model my CEngine that executes C source code without compiling to a CPU ISA and then having to simulate the CPU. To model an SoC the function of the Verilog modules is a set of classes and the SW is a set of classes that are compiled together.
The SoC is then just another C# program that runs in the VS IDE with all the debugging and editing available.
The problems are that it runs on a Windows instead of Linux and is based on logic design rather than Verilog inference/synthesis.
I designed a mini computer except for the ALU with only 1 missing inverter by designing the logic first as in this methodology so it does work. (This methodology would have found the missing inverter)
The modular classes in OOP are analogous to Verilog modules. Important features are that get/set access to class properties correspond to module input/output and assignment to variables corresponds to wire assignments in Verilog. The syntax differences can be handled by parsing source and generating different syntax. This is not C to Verilog -- it is using C to define the logic function and generating Verilog to express that same function.
I am using Visual Studio Express C# to model my CEngine that executes C source code without compiling to a CPU ISA and then having to simulate the CPU. To model an SoC the function of the Verilog modules is a set of classes and the SW is a set of classes that are compiled together.
The SoC is then just another C# program that runs in the VS IDE with all the debugging and editing available.
The problems are that it runs on a Windows instead of Linux and is based on logic design rather than Verilog inference/synthesis.
I designed a mini computer except for the ALU with only 1 missing inverter by designing the logic first as in this methodology so it does work. (This methodology would have found the missing inverter)
