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. Intel 18A, BEOL M0 36/32nm with EUV Low NA0.33 Single Exposure, announced by Intel
. TSMC N3/N2, BEOL M2 ~32nm with EUV Low NA0.33 Single Exposure? no announcement yet by TSMC
. below, SEM images by Nvidia & IMEC, cuLitho helps, link = https://arxiv.org/abs/2602.15036, 2026-Jan
. both Intel & TSMC using cuLitho (not for R&D but) for HVM already?
I don't think these are realistic patterns, with such large gaps between line ends. Are they leaving room for SRAFs? Aside from the long lines which look like they didn't clear, these could be stochastic occurrences. In that case, the effectiveness itself will be stochastic, since defect probabilities can themselves vary over an order of magnitude: https://frederickchen.substack.com/p/explaining-ppm-level-stochastic-defectivity