Assertion-first hardware design: where properties and intent come first

[AmandaK]

January 7, 2026

Compute is the bottleneck. Not ideas. Not talent. Compute.

Every major leap we care about over the next decade, from AI to medicine to energy and mobility, depends on chips that deliver more performance with less power, on tighter schedules than ever. RTL can be produced faster and faster, but one thing still dictates the pace: proving correctness. A recent SemiWiki article on LUBIS EDA makes the same observation: even if AI accelerates RTL creation, verification remains the hard requirement and the schedule risk.

The stakes: verification is still the bottleneck​

AI generated RTL may look plausible, but correctness in hardware is non negotiable. Chips must work under every possible condition, and relying on “looks right” is not enough. Using AI to verify AI does not remove risk, it can compound it, because failure patterns can align across systems trained on similar data. The conclusion is simple: verification continues to dominate cost and schedule because correctness requires precise, formalized intent.

The shift: from RTL first to assertion first​

Assertion IP captures intent in its most exact form. It describes how a design must behave across states, cycles, inputs, and transitions. In the ideal process, assertions come first, and RTL is implemented against them and proven against them. This is the approach we call assertion first hardware design: start from executable intent, express it as properties, and make correctness something you can prove from day one.

Why hardware has not started from assertions​

The problem was not the idea, it was feasibility. Writing a complete set of properties manually was slow and error prone, high level models were inconsistent and difficult to analyze, property generation tools did not exist, and formal engines were not strong enough to handle the depth and complexity of real IP blocks. So the industry normalized an RTL first culture, where assertions often arrived late and lived as an afterthought instead of the foundation.

What changed: why assertion first is now practical​

The landscape has shifted. Several advances now come together. High level model analysis can extract states, transitions, invariants, and dataflow from executable models such as C++ and SystemC. Automated property generation can transform those models into more complete assertion suites that also capture timing behavior and correctness requirements. Formal verification engines have matured to handle deeper pipelines and larger state spaces. AI assistance can make it easier to create structured models that are analyzable, by translating intent into code that tools can reason about. Together, this makes assertion first design far more practical than it was for decades.

Where LUBIS EDA fits​

At LUBIS EDA, we turn assertion first into a practical methodology and delivery model. We generate comprehensive Assertion IP from high level executable models, bridge the gap between abstract model and RTL implementation, and use refinement techniques so the properties align with cycle accurate, bit level RTL reality. On top of that, we provide formal verification services and training to help teams adopt assertion driven workflows and reach formal sign off on complex blocks.

Why this matters for chip teams right now​

Assertion first is not a slogan. It is a response to a structural reality: complexity rises, schedules tighten, and correctness expectations stay absolute. The only sustainable path is to move from formal as heroics to formal as a system, where intent is explicit, properties are complete, progress is measurable, and sign off becomes repeatable.

Summary​

If verification is the bottleneck in your program, whether you are expanding formal, struggling with coverage closure, or trying to make results predictable across projects, an assertion first approach is a practical way to change the curve. SemiWiki’s conclusion is that this paradigm is now within reach, and that LUBIS EDA is helping pry open the door to a future where hardware design can begin with formal Assertion IP.

Link to Press Release