Hello,
Are there tools that provide cost of various cost components (NRE & RE) associated with ASIC/SoC.
You may try the following to calculate NRE and RE cost for ASIC
RE (which is equivalent to cost to make one ASIC)
1. Calculate the die area. A die can be core limited or pad limited and die area will be larger of the core area or pad area. Core area will be a function of total gate-count, routing congestion achievable (depends on process nodes, frequency of operation, % of memory and analog macros in the design etc), area of memory, area of analog macros. Pad area will depend on number of signal and P/G I/O, type of IOs (different IOs like LVDS, DDR etc have different pitch), whether the IO has been put in linear or staggered manner, pitch restriction by chosen package etc
2. Wafer cost then needs to be calculated. Wafer price will depend on base wafer cost at the targeted process nodes, cost of additional metal layers, cost of special layer (like DNW, RDL etc). Then from wafer cost, die area and yield (function of process node, number of metal layer, die area, analog and memory % in the design) die cost needs to be calculated.
3. The die cost needs to be adjusted by wafer sort yield if wafer sort test is done
4. Then the packaged die cost needs to be calculated by adding package cost and test cost per die with the die cost and adjusting it by package yield (if wafer sort is done) or both package and die yield (if wafer sort is not done). Test cost per die is calculated from tester rental, number of test site, test runtime, test set-up time etc
The NRE depends on from what level of the SoC design you are calculating the cost. Let us assume the calculation starts from frozen RTL. Then NRE will constitutes of mainly
1. RTL to GDSII implementation cost - this will include total engineering cost as well as total EDA tool cost. Total engineering cost can be calculated from the cost of engineers and their effort. EDA tool cost can be calculated from number of license used, license cost. Off course not all licenses are used always for the design and hence one can amortize EDA tool cost across multiple projects if they are running in parallel. There will be some cost for the computing infrastructure also, but typically that is relatively smaller component
2. IP license cost - SoC typically uses significant IPs from third party and hence those IP license cost needs to be added. If the license deal is for single use then the cost will be loaded 100% for that particular SoC. But if the deal of multiple use then the cost can be amortized across multiple SoCs
3. Package and test NRE - This includes package design cost as well as one time cost to manufacture the package (like ball mount kit). Test NRE will depend on test program development and debug cost
4. Mask NRE - This will depend on base mask cost which depends on process node, additional metal layer mask cost, mask cost for special layer (line DNW, RDL etc)
Regards,
Barun Kumar De
