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"Our designs are asynchronous and resilient from the ground up, while still being compatible with existing CAD tools and software stacks. Traditional processors must complete an instruction within a specific clock cycle. This means clocks lead to wasted time."
"Our designs are asynchronous and resilient from the ground up, while still being compatible with existing CAD tools and software stacks. Traditional processors must complete an instruction within a specific clock cycle. This means clocks lead to wasted time."
The problems with RTL (synchronous logic) as a design methodology are numerous:
It burns power when there is nothing to do (unless you add clock gating).
Sub 45nm the high variability in device characteristics means you have to add slack (the "wasted time").
If you lower the voltage (to save power) it will miss timing, and fail - unless you do DVFS.
Large clock trees are hard to design and verify.
RTL itself is bad since you really shouldn't put the clocks in the design spec, a data-driven (asynchronous FSM) methodology is better for designers and tools - simulation tools burn a lot of time simulating clock related stuff that isn't really necessary for functional verification.
Unfortunately there isn't much compatibility between asynchronous logic and RTL when it comes to tools, anything above (fast) SPICE can't deal with variable voltage and timing (even for DVFS). Silistix found that out a while ago.
