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An open source PDK for 130nm process node

Scott Jones tracks 300mm and 200mm fabs so he would know the minute details. Not surprisingly 200mm fabs are still very profitable. Even TSMC does quite a bit of business at 200mm (6 fabs) and continues to invest.

TSMC Fab Capacity 2020.png
 
I find the whole thing both awesome and annoying at the same time. Here's the deal:
  • The process is an older 130nm process, which is perfect for big-A/little-D work.
  • The emphasis seems to be on logic chips.
Now, this is kind of understandable, really. The whole idea is to get open source tool flows working, and when it comes to open source tool flows, analog is not too well served.

It's actually an uneven situation. Where available FOSS tools do well for analog ICs is in simulation and GDS editing. Simulation has NGSPICE, GNUCap, Qucs, and Xyce. GDS editing has Magic, KLayout, and Xic. Where things get iffy are things like physical verification (DRC, LVS, and, especially, PEX), which is a problem shared with the digital flows. Another big failing is in waveform viewers, where it's hard to find a good viewer with delta markers and post-sim processing that can handle large files and the many, many plots analog design uses.

Perhaps the least expected failing, though, is schematic editing. Everyone will say, "but what about KiCad and CircuitLab and so on?" Well, those tools serve PCBs well, but ICs have a lot of hierarchy and reuse, which is best served by libraries of cells with multiple views. Last I looked, the only way to reuse a symbol you make for a subcircuit in KiCad is to copy it from one schematic and paste it in another. I also seem to recall KiCad has some limits on allowed levels of hierarchy that an analog IC designer would find onerous, but I may be wrong or out of date. I don't think there's any FOSS schematic editor that provides parameterized attributes, so your resistor symbol can calculate the resistance based on your L, W, M, and number of stripes; things like that. Now, that last one really shows the PCBness of the FOSS schematic editors, since PCBs present little need for attributes to be calculated from other attributes, even if only for convenience.

So, yeah, I'm psyched that there will be an open PDK that people can design chips with using FOSS tools, I just wish the analog tooling was built out well enough to fully exploit it.
 
You may want to check the design flow I have been working on, called Revolution EDA (RevEDA in short). It consists of Glade schematic/layout editor, Gemini DRC/LVS, Xyce circuit simulator and simulation GUI developed by me. Simulation GUI allows point-and-click selection of nodes and instances, saving of simulation state to a plain-text yaml file, backannotation of DC voltages, plotting of device parameters. It also has callback routines to define the layout dependent parameters in schematics. DC, AC, TRAN and Noise simulations are already possible. The RF performance measures such as IP1dB, IIP3 and IIP2 based on Xyce harmonic balance simulations are almost ready. Once S-parameter simulations were added, it would amount to a complete solution targeting custom IC design. I already created a short video to summarise its status:

 
revsemi said:
You may want to check the design flow I have been working on, called Revolution EDA (RevEDA in short). It consists of Glade schematic/layout editor, Gemini DRC/LVS, Xyce circuit simulator and simulation GUI developed by me. Simulation GUI allows point-and-click selection of nodes and instances, saving of simulation state to a plain-text yaml file, backannotation of DC voltages, plotting of device parameters. It also has callback routines to define the layout dependent parameters in schematics. DC, AC, TRAN and Noise simulations are already possible. The RF performance measures such as IP1dB, IIP3 and IIP2 based on Xyce harmonic balance simulations are almost ready. Once S-parameter simulations were added, it would amount to a complete solution targeting custom IC design. I already created a short video to summarise its status:

Click to expand...
FYI, links to the EDA tools:

Glade: https://peardrop.co.uk/

Gemini: https://www.cs.washington.edu/research/gemini-netlist-comparison-project

Xyce: https://xyce.sandia.gov/
 
The beauty of it is that everything is run through Glade's built-in python interpreter. A huge improvement in coding productivity compared to the scripting languages in commercial tools.
 
For anybody interested, you could see the latest status of Revolution EDA in these Youtube videos:

The next video will cover the layout using Sky130 process technology including parametric cells for transistors and resistors.
 
In this video, I showcase the Sky130 process parametric cells and layout generation from schematic in Glade.
 
Hi revsemi,

How can these Revolution EDA tools Glade schematic/layout editor be installed alongwith sky130 pdk. Please share some more details.
 
Hello,
I am planning to release Glade/Revsemi combo with preliminary Sky130 support. I am afraid that it will not be free/open-source software though. However the cost will be around one fiftieth (1/50) cost of big names.
 
Last edited:
revsemi said:
Hello,
I am planning to release Glade/Revsemi combo with preliminary Sky130 support. I am afraid that it will not be free/open-source software though. However the cost will be around one fiftieth (1/50) cost of big names.
Click to expand...
By when is it expected to be released and how can update on same be received.
 
Hello engrvip,

I expect to have it ready in a few months. Is there a format such as a container you prefer?
 
revsemi said:
Hello engrvip,

I expect to have it ready in a few months. Is there a format such as a container you prefer?
Click to expand...
Hi,

Could not understand what is meant by "format such as container" in your last reply. Can you please elaborate.

I am interested in exploring open-source EDA flow for working with sky130 pdk. But current set of eda tools don't seem very convenient and aslo do not have features like HB analysis. That's where Glade seems to have edge and made me interested in exploring it.
 
I meant something like a docker container including all the components of RevEDA: Glade, Xyce, Simulation GUI, PDK, etc. It seems that it could save some headache in setting it up. The problem is that the size is around 2Gb. With today's high-speed connections, it does not seem to be a significant problem.
To clear the confusion, it will not be open-source unless it uses software that has an open-source licence, but very low-cost.
 
Revolution EDA Preview release is out as a docker image. This release has a six-months free license until 31-05-2022. Docker setup files and installation instructions for Windows machines are in a GitHub repository. You could also file issues for any bugs or feature requests in the same repository.
github.com

GitHub - eskiyerli/revEDAsetup: Revolution EDA container image setup files

Revolution EDA container image setup files. Contribute to eskiyerli/revEDAsetup development by creating an account on GitHub.
github.com github.com

The download is a 1.5GB docker image and when extracted is around 4.7GB. To run it on a windows machine, you would need Docker Desktop for Windows and VcXsrv X11 display server for windows.

This release includes:
  1. 1. Glade schematic and layout editors.
  2. 2. Xyce circuit simulator including direct access to AC, TRAN, HB, NOISE and DC analyses. SP analyses will be added soon.
  3. 3. Revolution EDA simulation GUI including:
    1. a) Point-and-click drawing of waveforms
    2. b) More than 20 performance parameters related to AC, TRAN, NOISE and HB analyses.
    3. c) Sweep of circuit parameters in steps or by choosing particular values.
    4. d) The order of sweeps can be changed.
    5. e) Process corners in the model libraries can be chosen.
    6. f) Node voltages, currents, some element values and small-signal parameters can be saved to be plotted after each simulation run.
    7. g) Simulation options such as transient integration methods, etc can be changed.
  4. 4. Revolution EDA Waveform plotter with a notebook interface.
  5. 5. GCC and ADMS for inclusion of Verilog-a behavioural models.
  6. 6. Revolution EDA Verilog-a model importer and symbol generator.
  7. 7. Example Sky130 process symbols with callback functions.
  8. 8. Example Sky130 process layout parametric cells.
  9. 9. Example Sky130 process substrate taps and vias.
This release does not include:
1. DRC and LVS functions. They will be provided on for a later release if there is demand.

There is a YouTube channel demonstrating the use of Revolution EDA flow:
 
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