The South Korean chipmakers accelerate shift to vertical DRAM architecture
By Chun Byung-soo,
Kim Mi-geon
Published 2025.06.18. 11:35Updated 2025.06.18. 14:42
Samsung Electronics and SK hynix are accelerating the development of next-generation three-dimensional (3D) dynamic random-access memory (DRAM), with both companies aiming to complete and test early prototypes of vertically structured “4F² DRAM” by the end of this year, according to industry sources.
The 4F² DRAM architecture marks a departure from conventional planar DRAM, adopting a vertical stacking approach to overcome the miniaturization limits of existing structures. The design is expected to deliver improvements in performance, data transfer rates, and energy efficiency. Both Samsung Electronics and SK hynix are positioning 4F² DRAM as a transitional step toward full-fledged 3D DRAM technology.
DRAM stores information in units known as cells, with the area of each cell typically represented as F². The standard architecture to date has been the 6F² cell, featuring three vertical bit lines and two horizontal word lines. The 4F² concept reduces both to two lines, while positioning the transistor—the functional switch within each DRAM cell—vertically to increase density and shrink chip size.
As of June 18, both South Korean chipmakers are reportedly expediting efforts to develop operational 4F² DRAM prototypes. “Ahead of entering full-scale 3D DRAM development, the companies plan to complete and validate 4F² DRAM prototypes capable of actual operation within the year,” said one semiconductor industry source. “Once commercial feasibility is confirmed, they intend to advance into 3D DRAM based on this structural foundation.”
In contrast, U.S.-based Micron Technology is said to be skipping 4F² DRAM altogether, opting instead to move directly into 3D DRAM development.
Samsung Electronics and SK hynix have been seeking architectural alternatives amid growing challenges associated with planar DRAM scaling. As the linewidth of circuitry narrows, integration density increases, resulting in improved performance and power efficiency. Currently, Samsung, SK hynix, and Micron are competing with DRAM products built on 10-nanometer-class process nodes. The most advanced product thus far is sixth-generation (1c) DRAM. However, attempts to scale below the 10-nanometer threshold have driven up technical complexity and manufacturing costs, leading to widespread recognition that a shift in DRAM architecture is necessary.
In response, memory chipmakers are pivoting toward vertical designs to extend the performance curve beyond the limits of planar scaling. Samsung is expected to roll out 4F² DRAM following its seventh-generation (1d) 10-nanometer-class products, while SK hynix is likely to introduce its 4F² variants in the subsequent generation. If development proceeds as planned, vertically structured DRAM could enter mass production within the next three years. Performance gains for 4F² DRAM are projected to approach 50 percent over current models.
The architectural transition is also expected to reshape manufacturing processes, materials, and equipment requirements. Samsung Electronics and SK hynix are collaborating with global semiconductor equipment makers, including U.S.-based Applied Materials, to co-develop the advanced processes necessary for 4F² DRAM fabrication. Given the heightened technical demands, both companies are focused not only on product development but also on establishing stable and scalable manufacturing infrastructure.
“Planar DRAM miniaturization is becoming prohibitively expensive, and there’s a critical need to boost performance,” said Lee Byung-hun, professor of semiconductor engineering at Pohang University of Science and Technology (POSTECH). “At this point, transitioning to vertical DRAM architecture is seen as the only viable path forward. However, given the scale of structural change, both development and manufacturing processes will face considerable challenges.”
Samsung and SK hynix advance 4F² DRAM as gateway to 3D memory
By Chun Byung-soo,
Kim Mi-geon
Published 2025.06.18. 11:35Updated 2025.06.18. 14:42
Samsung Electronics and SK hynix are accelerating the development of next-generation three-dimensional (3D) dynamic random-access memory (DRAM), with both companies aiming to complete and test early prototypes of vertically structured “4F² DRAM” by the end of this year, according to industry sources.
The 4F² DRAM architecture marks a departure from conventional planar DRAM, adopting a vertical stacking approach to overcome the miniaturization limits of existing structures. The design is expected to deliver improvements in performance, data transfer rates, and energy efficiency. Both Samsung Electronics and SK hynix are positioning 4F² DRAM as a transitional step toward full-fledged 3D DRAM technology.
DRAM stores information in units known as cells, with the area of each cell typically represented as F². The standard architecture to date has been the 6F² cell, featuring three vertical bit lines and two horizontal word lines. The 4F² concept reduces both to two lines, while positioning the transistor—the functional switch within each DRAM cell—vertically to increase density and shrink chip size.
As of June 18, both South Korean chipmakers are reportedly expediting efforts to develop operational 4F² DRAM prototypes. “Ahead of entering full-scale 3D DRAM development, the companies plan to complete and validate 4F² DRAM prototypes capable of actual operation within the year,” said one semiconductor industry source. “Once commercial feasibility is confirmed, they intend to advance into 3D DRAM based on this structural foundation.”
In contrast, U.S.-based Micron Technology is said to be skipping 4F² DRAM altogether, opting instead to move directly into 3D DRAM development.
Samsung Electronics and SK hynix have been seeking architectural alternatives amid growing challenges associated with planar DRAM scaling. As the linewidth of circuitry narrows, integration density increases, resulting in improved performance and power efficiency. Currently, Samsung, SK hynix, and Micron are competing with DRAM products built on 10-nanometer-class process nodes. The most advanced product thus far is sixth-generation (1c) DRAM. However, attempts to scale below the 10-nanometer threshold have driven up technical complexity and manufacturing costs, leading to widespread recognition that a shift in DRAM architecture is necessary.
In response, memory chipmakers are pivoting toward vertical designs to extend the performance curve beyond the limits of planar scaling. Samsung is expected to roll out 4F² DRAM following its seventh-generation (1d) 10-nanometer-class products, while SK hynix is likely to introduce its 4F² variants in the subsequent generation. If development proceeds as planned, vertically structured DRAM could enter mass production within the next three years. Performance gains for 4F² DRAM are projected to approach 50 percent over current models.
The architectural transition is also expected to reshape manufacturing processes, materials, and equipment requirements. Samsung Electronics and SK hynix are collaborating with global semiconductor equipment makers, including U.S.-based Applied Materials, to co-develop the advanced processes necessary for 4F² DRAM fabrication. Given the heightened technical demands, both companies are focused not only on product development but also on establishing stable and scalable manufacturing infrastructure.
“Planar DRAM miniaturization is becoming prohibitively expensive, and there’s a critical need to boost performance,” said Lee Byung-hun, professor of semiconductor engineering at Pohang University of Science and Technology (POSTECH). “At this point, transitioning to vertical DRAM architecture is seen as the only viable path forward. However, given the scale of structural change, both development and manufacturing processes will face considerable challenges.”
Samsung and SK hynix advance 4F² DRAM as gateway to 3D memory