You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!
Products exposed as test vehicles.
At the April 15 earnings call: https://www.morningstar.com/stocks/xwbo/asml/earnings-transcript, what he said was this:
Yeah, I think, Francois-Xavier, I think it's a bit too early to answer the question. I think what we see today is that several of our...
At the last conference call, he said it was not prime time for High-NA. Customers were still evaluating how to use in production. That should mean using product patterns as test vehicles.
A big fundamental difficulty is the reduced depth of focus. That's what happens when you use higher NA...
Founded in 2016, CXMT is widely regarded as China’s only domestic DRAM maker to have achieved mass production
Howard Liuin Beijing
Published: 7:30am, 14 May 2026
Chinese memory module manufacturers are accelerating the release of consumer and enterprise storage products powered by domestic...
At IMW, it was revealed these 8-high+logic die stacks are turned on their side and stacked laterally as tiles to form an inductively coupled network of tiles.
4F2 comes in after 1d, but only lasts three generations. Since resources are being spent on 1d, 4F2, of course the 3D DRAM progress would be slowed down, but that only applies to the Samsung and SK hynix and maybe Micron. 3D DRAM is a long-term solution for the tier-1 guys but probably the big...
This would be true for Samsung, SK hynix, etc. but it might be very different perspective for CXMT for example. CXMT is likely to skip 2D nodes going forward.
CXMT first discussed their 3D DRAM at IMW 2023: https://ieeexplore.ieee.org/document/10145931
Abstract:
Continuous shrinking of dynamic random access memory ⟨DRAM) feature size will inevitably hit unsurmountable barriers, such as sub-10 nm patterning issues, ultra-high aspect ratio (HAR)...
From the abstract:
Buried multilayer (ML) defects in EUV masks continue to pose a significant challenge to imaging fidelity and yield in 0.33 NA EUV lithography.
However, it's only going to get worse with High-NA, which collects more light from smaller defects...
The 3D DRAM in principle reduces the rowhammer risk with larger separations between word lines, but the JEDEC standard of 32 ms may be locked in at that time. The refresh rate is not that high a priority for scaling.
The scaling will be most strongly impacted by distances within the DRAM cell itself. The VCT 4F2 architecture is motivated by the bit line approaching the capacitor active area contact too closely, while the 3D DRAM architecture comes from the capacitor itself becoming too thin.
For DDR5/LPDDR5, refresh rate doubled from every 64 ms to every 32 ms. I'm pretty sure rowhammer had a lot to do with it. So this basically affects 1b onwards, although the issues started as early as 2x nm I'm sure.
Author: Su Ziyun | Publication Date: April 16, 2026, 12:13 PM
According to Wccftech, Qualcomm is collaborating with Chinese memory manufacturers Changxin Memory and GigaDevice to develop a standalone neural processing unit (NPU) that incorporates 3D DRAM, attempting to overcome the current...
