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CXMT is providing decent DDR5, although the notorious price drop from some weeks ago is now no longer the case.
The DDR5 nightmare hasn't eased yet, but today we're checking out an option that might be viable for anyone who needs to get their hands on some memory.
As we're all painfully aware...
I had heard about ANAFLASH's 28nm edge AI project back in November: https://www.businesswire.com/news/home/20251103252346/en/ANAFLASH-Advances-Embedded-FLASH-Memory-for-Next-Generation-Smart-Edge-Devices-with-Samsung-Foundry
I'd be curious and eager to know if their 8nm eMRAM gets any design...
Jukan's source for this post is a ZDNet article: https://zdnet.co.kr/view/?no=20260225154303#_enliple
Samsung Electronics' breakthrough was the "enlargement of the chip size" of its 1c DRAM. Around the end of 2024, Samsung Electronics decided to revise some of its 1c DRAM design. The key point...
Samsung Electronics made the decisive move to enlarge the die size of its core die, the 1c (6th-generation 10nm-class) DRAM. A larger die size can simultaneously improve the stability of both DRAM and HBM4.
However, this decision works unfavorably from a profitability standpoint, as it reduces...
We've heard that 18A yields were still on improvement path toward the end of 2025. Parametric yields could also result from stochastics as manifested in uniformity. But EUV yield is intrinsically erratic, since the D0 (from stochastics) can vary over an order of magnitude.
If Backside or GAA/RibbonFET are new sources of yield loss, then relaxing to 36 nm pitch looks understandable. That said, high defect density at 36 nm pitch has been noted publicly before by imec, Samsung, and even (indirectly) TSMC.
Did Intel just delay their 14A node by a year?
At Cisco's AI Summit this month, Intel CEO Lip-Bu Tan announced that Intel's 14A node will be in risk production in 2028 and volume production in 2029, representing a 1 year slip from prior disclosures of a 2027 risk production start date. The...
Yes, a 32 nm pitch direct EUV print is highly risky and ppm-level defect probabilities have already been reported in several published sources (besides myself, Samsung/ASML and imec/Siemens) for 40 nm pitch and below. Probably even more difficult is the wide range (over an order of magnitude) of...
Ok, I'm not sure if the author is doing solely a speculative analysis or has the teardown. Author mentions five M0 tracks, but the cell height is determined by six 38 nm pitch M2 tracks (=228 nm).
I had the understanding that TechInsights did the analysis for this, so I'm not sure if that is...
