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The EUV argument starting 12:20 falls apart when you consider Samsung.
I was also surprised by his characterization of US perception of manufacturing as a non-prestigious "blue-collar job" 17:40.
AI chip design startup, Tenstorrent, has announced it's working with a range of companies to build out its next-generation AI chips. These include TSMC, Samsung, and Japanese firm Rapidus, all of which will provide their latest 2nm process nodes to develop future AI hardware. CEO and AMD and...
To their credit, Intel has been a sort of guinea pig for High-NA EUV. Here's what they disclosed:
"The High NA POB (Projection Optics Box) is so large, it is not feasible to test and adjust the POB to final spec at the supplier. This means that initially the system will be shipped with a POB...
By Pablo Valerio 10.01.2025
The global semiconductor industry is undergoing a profound economic transformation, one anchored by Taiwan Semiconductor Manufacturing Company (TSMC) that spells the end of an era defined by predictably declining costs of transistors.
At the center of this...
6 months ago, AMD announced it was TSMC N2 first HPC customer and also a customer for TSMC Arizona: https://www.amd.com/en/newsroom/press-releases/2025-4-14-amd-achieves-first-tsmc-n2-product-silicon-milesto.html
But AMD CEO Lisa Su also mentioned that TSMC Arizona is 5%-20% more expensive than...
The 4F2 vertical channel scheme is still continued scaling of bit line pitch (which increases its capacitance relative to capacitor) but the slanted active area pattern is gone, and the buried word line now becomes a side word line. It is projected to only be used for three years (three nodes)...
I was looking over some of Intel's recent SPIE papers from within the past year. ASML/Zeiss can't measure the High-NA EUV system aberrations at their own site (too big), they have to do so at the customer site. That means all High-NA systems are basically shipped out of spec, and one or more...
The thinning of the dielectric between bit line and storage node contact results in rapidly growing parasitic capacitances and leakage. So this is the problem with current planar 6F2 DRAM. 4F2 DRAM offers a way out but capacitor patterning is still a problem and more than one stacked layer is...
The three companies have taken different paths, not just in EUV deployment. The shrink from 1a to 1b (14nm to 12nm) is larger than from 1b to 1c (12nm to 11nm). So the EUV is not a big help in this regard.
There's some more on the differences among the N7 processes here: https://www.eettaiwan.com/20200115nt61-7nm-comparision/ although N6 was not out yet it seems. But there's actually an N7P different from N7+.
I just checked TSMC's site now, it seems to be consistent with as you say:
https://www.tsmc.com/english/dedicatedFoundry/technology/logic/l_5nm
In 2020, TSMC became the first foundry to move 5nm FinFET (N5) technology into volume production and enabled customers’ innovations in smartphone and...
It's based on a cryogenic spintronic device. IMEC had been fabricating the chips for them. It looks like electron-beam lithography is still being used on these demo chips. I think it's because the volume is not enough to justify making a set of masks.
