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That report on SK hynix conflicts with this one: https://semiwiki.com/forum/threads/sk-hynix-builds-m15x-test-line-to-respond-to-hbm-demand.23690/
Historically, actual recognized sales has been lower than these forecasts.
ASML shipped five EXE:5000 and one EXE:5200 as of the Q2 2025 earnings call. The EXE:5200 may still be considered a development tool if it is the only High-NA capable of delivering higher power (for higher dose at sufficient throughput) and/or sufficient overlay. The EUV-induced plasma would be...
The trend has been wafer cost up, yield down, SRAM doesn't scale, gate pitch hasn't scaled well either. I think track pitch is starting to slow down as well now as approaching 20 nm.
For DRAM, smaller capacitors need to be relatively taller, otherwise they become swamped by parasitic...
The emergence of high-NA EUV lithography has intensified mask 3D effects, necessitating advanced cleaning solutions for next-generation mask components. Removal of tin (Sn) particles is crucial for maintaining mask performance, as Sn is used to generate EUV light and continuously contaminates...
SK hynix will build a 10nm 5th generation (1b) DRAM production line with a capacity of 10,000 wafers per month at the Cheongju M15X fab. As it is a test line, if mass production is approved, full-scale investment will begin. It is expected that equipment will begin to be brought into M15X as...
This looks very relevant: Real-time observation of EUV-induced blister formation at various sample temperatures in pellicle-like materials
In this study, we investigated degradation mechanisms on pellicle-like, semi-amorphous, 50 nm SiN thin films exposed to both isolated hydrogen radicals and...
Josephson junctions may use e-beam lithography: https://patents.google.com/patent/US20180013052A1/en
I suppose the low volume and small chip size justifies the use of e-beam (short write time), but I imagine they could alternatively use i-line (365 nm) lithography with spacers for higher volumes.
In 2006, Intel talked about a non-removable pellicle "as a backup approach to the pellicle-less methods pursued by suppliers and EUVL partners." The paper is here: EUV Pellicle Development for Mask Defect Control. If they're using pellicles now, it would have to be the one from Mitsui (which...
ESOL's position is interesting. I imagine its customers will be EUV mask shops. But complete pellicle testing still requires it to be immersed in the hydrogen plasma of an ASML EUV machine.
More interesting details here: https://www.sisajournal-e.com/news/articleView.html?idxno=414355
They now are doing dual exposures with EUV.
Indeed, it's surprising they don't also apply this to memory; what's not being said tells more.
It's the sparse patterns.
Sep. 18, 2025 2:21 PM ET
By: Brandon Evans, SA News Editor
Nvidia (NASDAQ:NVDA) CEO Jensen Huang said Taiwan Semiconductor Manufacturing (NYSE:TSM) will provide the foundry support for the "revolutionary" chips they are making with Intel (NASDAQ:INTC).
"Nvidia and Intel are both successful...
"PSM" may not be an appropriate term for EUV masks anymore, since the light goes through a phase shift dependent on angle and pattern just from the EUV multilayer itself. There has been substantial work on low-n absorbers, but the benefits, again, appear pattern-dependent.
