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Commercial tandem perovskite/silicon cells are currently at 27%...
https://www.pv-magazine.com/2025/04/09/oxford-pv-trina-solar-enter-patent-licensing-agreement-for-perovskite-silicon-tandem-solar/
Not for real commercial use, performance increase rate has slowed to a crawl for big-volume affordable cells. Solar cell efficiency is limited by physics, unlike semiconductors where most of the improvements come from ever-smaller transistors but this has no relevance to solar cells.
Cost...
Just like batteries, that's what a lot of the "SOLAR CELL BREAKTHROUGH!!!" promoters fail to understand -- no matter how good the efficiency is in the lab, it'll never make it out into widespread use in the real world unless the cells can be made cheaply in massive volumes and don't need any...
Only for ludicrously complex and expensive multi-layer cells in the lab, using exotic materials -- there's zero chance of these ever getting into mass production for grid power generation, where cost per kWh is the most important factor.
The most promising cells for this are dual-layer...
Except that's misleading, they're 14% efficient which is 93% of the theoretical limit for perovskite cells -- but still only 60% of what monocrystalline silicon cells in mass production already achieve...
Are those sizes raw memory cell array or overall area including peripheral circuits (decode/sense/drive/muxing)?
I seem to remember seeing elsewhere that these numbers weren't apples-to-apples, TSMC figure was net (including peripheral) and the others were gross (memory cell only), and that in...
Yes, that's what I was referring to. Another article (can't remember where from) said that this had to be done by resorting to the equivalent of coding in assembler, it isn't possible in CUDA which is a high-level language.
Though presumably there would be nothing stopping Nvidia adding such...
You're missing what is probably responsible for a large part of the improvement, which is reprogramming 20% or so of the GPU engines to build a super-fast on-chip comms/sync network and reduce the effect of restricted inter-chip bandwidth. AFAIK this has not been done before, and it's not...
The problem for Intel is that nowadays "tech leadership" doesn't mean what you seem to think it does... ;-)
It doesn't mean having the sexiest most advanced technology on a Powerpoint slide, or even in a pre-production fab -- it means being able to mass-produce it in megafabs with good yield...
That's a "how long is a piece of string?" question... ;-)
Any redesign/port takes a lot of time and effort and money, which will be considerably smaller if the libraries/processes are compatible.
The second one is a commercial question, you'd need to ask TSMC. Could be positive, could be...
I believe that's the case, going by what was said in an earlier post (I've only seen N2 libraries) -- the N2 and A16 library cells are the same (same height and number of tracks), the difference is that with N2 you then define a conventional power mesh above them which competes for space with...
As far as the raw silicon technology is concerned TSMCs BSPD approach is more advanced than Intel's, they bring the power up directly under the transistors. They can presumably accept the added risk (or cost?) because A16 is a "premium" follow-on process to N2, so there's a fallback option for...
I thought that with A16 the TSVs came up directly underneath the transistors (bottom-side contact) instead of up into a "NanoTSV" and then sideways into the transistor like Intel?
Same alignment problem (top-side vs. backside) but in theory more efficient/advanced -- though this advantage (more...
I didn't say the hot-spot numbers I gave (+30C hotter) applied to all devices, they were an extreme case for local hotspots in small circuits with very high power density (can be up to 100W/mm2) not standard digital -- for example, inside the circuits used for 224Gbps SERDES which are clocked at...
Thanks for the clarification. I can see why Intel "BSPD-only" has an area advantage over TSMC "BSPD compatible with FSPD", but doesn't that also make an assumption about how the BSPD contacts are made -- I thought that Intel's were offset from the transistors which means they need some extra...
I agree that the Intel slides look good... :)
Whether this actually means their process is "better" or "worse" for PPA than TSMC in reality (as opposed to Powerpoint-world) very much depends on the assumptions and test cases that were used to generate those slides, as I tried to explain...
I'm not sure what you mean by "partial BSPDN" on A16 -- AFAIK it's at least technically comparable to 18A and possibly ahead, though the devil is in the details.
Whether 18A has a clock speed advantage and N2 a power/area one will very much depend on which libraries (and whose!) are used for...
