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You are correct - I overstated the case. OEMs are the unsung heroes in this thing. As to your larger point, the US is an innovator but it's weak in implementation in terms of actual chip making. Blame high costs, blame Wall Street, blame business models, blame all three!
If you think about...
@jms_embedded The article by Williams and Khan is very good. You can see the consensus building. The critical comments about the science policy approach of the 90s (the so-called road map that we all followed) was most interesting. The establishment of NSTC could lead to the same outcome and not...
Because CHIPS is driven by National Security considerations, issues of the past (when defense purchases were larger as a %) get conflated with issues of today (AI for military purposes could become a strategic weapons systems according to some analysts). In other words:
1- Defense was a big...
@jms_embedded Thanks a lot. Very enlightening. This is what I had written but without data to back it up:
The military was an early adopter of solid-state technology, first in guidance systems and radio, and gradually into everything else. In early years, chips sold for military applications...
Thanks - I will make sure I read it. I think that going forward, the US military is concerned about maintaining its dominance indefinitely, particularly in the area of AI (for pilotless fighters for example - there are many others). AI is done with chips so you need to restrict chip sales (the...
@Tanj I had the wrong official title! This is the real title: Unintended Consequences of Government Subsidies on Moore’s Law and the Future of Semiconductors... Sorry for the error. See you in Saratoga I hope.
CHIPS refers to the US subsidy program. Nothing to do with ICs! You will need to attend ASMC to find out but I suspect the panelists will say that it may not be a good idea to build factories in high cost areas (e.g. the US) as it could end up weakening the underlying companies and limiting...
@Tanj My full sentence should have read "plenty of customers so that the factory(ies) is full all the time". In my mind, with the new mega factories, this implies being a foundry unless Apple is your customer and they buy 100% of your output. Intel's model relies on building large factories but...
@Tanj Thanks for that. Good insights. Much of the rhetoric in the USA is that invented the transistor, we invented the IC, DRAM, etc. That is true but is tangential to the requirements of successful manufacturing in today's world: large factories, plenty of customers to full all the time (so...
I am in charge of upcoming ASMC panel discussion. We are bringing together experts to talk about "unintended consequences of CHIPS on Moore's Law". I need to put together a few strong graphics but I am having difficulty locating long-series data. Here is specifically what I am looking for:
1-...
That's where P1, P2 etc. come in. You have effectively separate factories sharing staff and utilities. I think that logic and memory have different optimum sizes BTW.
Because you have other tools in between the tools and because fo dispatching with re-entrant flows. Example of tool between tools: CD-SEM or cleaning tools. You are trying to minimize the overall travel time on average. Say you go from Litho to PVD to Plating to CMP to Clean, the position...
Excellent feedback. You placed me on another related track. The transit time to go between tool A and tool B is another important metric. Adding steps increases that time and making the fab infinitely large would also increase that transit time.
Like everything in our business, it's delicate...
Good point, thanks.
To summarize, we have # of wafers, yield, # of steps and linewidth. Competitive foundry would need to optimize the first 3 (leaving litho aside for now). So I want the yield to be as high as possible with the least # of steps (not too many cleans for example), making sure...
So one could get by at 1000 wafers per day BUT in reality, it would need to be larger to be competitive. This reminds me of the new Bosch fab in Dresden. Very small and probably not cost effective BUT good leverage when negotiating with Infineon or anyone else.
Agreed on non-linearity of...
That's smaller than I thought. TSMC 15P1 and P2 seemed much larger than 850 wpd each but i could be wrong. The total # of steps is another important variable. Total wafer-steps may be a more accurate way to think about it. If I do 5 nm, I have more steps than 28 nm so I will be able to output...
I need help from the community for an upcoming event (ASMC).
Considering the cost of land, of equipment etc. what would be the size of a generic competitive logic foundry being built today? TSMC is often confusing the issue by not calling each fab complex with its own name. So you end up with...
@Xebec There are parallels but there are also differences. The car business is mature in the sense that the optimal factory size is by now well known and that car prices increase each year or at least stay the same. The IC business has a growing factory size and a dropping ASP. If a factory did...
One final thought: DoD needs a stable supply of cutting edge chips (albeit in low volume) and they seek to DENY that same supply to foes. Money does not come into it from their point of view. Taiwan is not a foe but it could be hobbled in by blockade or hot war. We must keep this in mind when it...
